Question Raptor Lake - Official Thread

[dullard]

Is it impossible to design PMICs below 40nm?

One of the causes of the shortage is design trends that have changed over the last 2 decades. I have designed a few PCBs, but I have reviewed the designs of dozens more for medical instruments. When I started, the concept was to generate the voltages (12V, 5 V, 3.3 V, -5 V, -15 V, etc.) once (such in a power supply), route all kinds of voltages around to various parts of the equipment, and then have lots of capacitors at the place of use to hold those voltages steady.

Now the design trend is to generate one voltage (such as 12 V in a power supply), route only that 12 V around the equipment, and then have tons of PMICs, one at each place of use, creating just the voltage you need where you need it. Instead of a single PMIC, the last piece of equipment I reviewed had dozens of them.

 

[igor_kavinski]

...then have lots of capacitors at the place of use to hold those voltages steady.

Instead of a single PMIC, the last piece of equipment I reviewed had dozens of them.

So PMICs are being used because they are smaller than capacitors? Or relatively cheaper?

 

[dullard]

So PMICs are being used because they are smaller than capacitors? Or relatively cheaper?

There are several reasons.

• Capacitors are usually the part that historically fail a lot. So much equipment (especially TVs) are thrown away, when you can just open up a panel with a few screws, replace the bulging capacitor, and it is good as new.
• It is cheaper, easier, and more compact to run one high voltage line than several lines all at different voltages.
• Problems are isolated. Suppose there is a problem like a short on one component. If that component was connected to the same power line as everything else, then everything loses power. But with a bunch of power management chips around, only that shorted component is affected. Hypothetical example: if one of your computer drives fail, do you want to be able to use any of the rest of the computer or have it just be totally inoperable?
• Currents are lower. If you need 1 A of 5 V power, you can transmit 0.42 A of 12 V power instead and convert it to 5 V right where you need it. That means smaller wires can be used and/or less resistive heat is produced.

 

[Doug S]

The "12 volts everywhere" thing is why cars need so many PMICs, since they use more and more components (not just the ever increasing number of SoCs, but stuff like LCD displays, LEDs for lighting, etc.) that require lower voltages than the 12 volts run everywhere in the car.

Back when cars were all analog (or all analog except for maybe the ECU and stereo head unit) you could just build everything from lights to gauges to the cabin air fans to all run on 12v so voltage conversion wasn't necessary. Going digital and having PMICs everywhere does have the advantage that they no longer need be wedded to 12v, so they can use 48v in the future instead for greater efficiency and thinner wiring (save weight, cost)

Everyone previously just assumed that PMICs were a commodity, they will always be able to get as many as they want whenever they want...

 

[LightningZ71]

48VDC has been coming "any day now" to cars for decades...

 

[IntelUser2000]

But, your all E core idea is a good idea for certain use cases. That is why Intel is pursuing that idea with Sierra Forest with rumors of 128 E cores.

It doesn't have to be 1.25x the area, because if they are designing a new SoC with all E cores, things can be moved around to optimize for it. Right now I bet you there's a fair bit of empty space cause you are trying to fit differently sized rectangles into a one large rectangle.

Also Sierra Forest with Intel 3 in 2024 is definitely going above 128 E cores. I'm expecting 256 or even more. If we're expecting Granite Rapids to be at least 120 cores, then 120 E cores on the same node is kinda underwhelming. By pure ratio of core sizes, we should expect something like 384 cores.

Crestmont is probably going to outperform Sunny Cove in perf/clock and it's something they'll need to go against 2024 competition.

So PMICs are being used because they are smaller than capacitors? Or relatively cheaper?

Beancounters. That's it.

All this talk about being more reliable hasn't resulted in anything more reliable because they take more reliable components and use it to save on costs instead. So you end up being the same, or even worse than before.

Case in point when I bought a broken e-bike to fix. I noticed the MOSFETs for the power controller short circuited. The datasheets showed 56V for the maximum, while the battery is rated 44V, or 12 LiPo cells. Well, when fully charged, the 12 LiPo cells would reach 51.2V, dangerously close to the absolute maximum rating of the MOSFET.

I bet over time it got degraded to the point where it went down to 51V. We're talking about an e-bike that would have cost $3,000+ US when new.

20 years ago, they didn't design it that way. Sure the technology improved but the mindset went the opposite. Most prevalent among Chinese vendors, but rest of the world adopts it to compete.

Same with SSDs using "no moving and reliable parts" but they turn it around to save on cost.

Also the faux green movement doesn't help. Lead-free solder is brittle, unlike leaded solder. And they can create solder whiskers, and short out components over time.

If they were really being "green" they would make it more repairable, and make things like laptops more modular. Companies like Apple penalized repair shops for years now.

 

[Exist50]

Also Sierra Forest with Intel 3 in 2024 is definitely going above 128 E cores. I'm expecting 256 or even more. If we're expecting Granite Rapids to be at least 120 cores, then 120 E cores on the same node is kinda underwhelming. By pure ratio of core sizes, we should expect something like 384 cores.

I don't want to get too OT, but I wonder about this. They have 1 node shrink, and likely 2 generations of architecture improvements to support. Going to depend a lot on what the design goals are for Atom.

 

[IntelUser2000]

I don't want to get too OT, but I wonder about this. They have 1 node shrink, and likely 2 generations of architecture improvements to support. Going to depend a lot on what the design goals are for Atom.

They may not get the full two generation for shrinks, but the performance gains between 7 and 3 is a massive 40%.

Also I doubt we'll see two generations. Atom gets 1 big jump every 2 years rather than smaller ones every year. Raptorlake gets a Gracemont refresh pretty much. Meteorlake gets Crestmont but that's 2H 2023. That's way too early, and this doesn't even factor in server cores taking longer than client.

 

[mikk]

They may not get the full two generation for shrinks, but the performance gains between 7 and 3 is a massive 40%.

Also I doubt we'll see two generations. Atom gets 1 big jump every 2 years rather than smaller ones every year. Raptorlake gets a Gracemont refresh pretty much. Meteorlake gets Crestmont but that's 2H 2023. That's way too early, and this doesn't even factor in server cores taking longer than client.

2023 Meteor Lake= Crestmont
2024 Arrow Lake= Skymont

Sierra Forrest is scheduled for 2024 same as Arrow Lake, so there is a chance it comes with Skymont E-cores rather than Crestmont. And Arrow Lake was planned for Q4 2023 until they went from TSMC 3nm to Intel 20A.

 

[Exist50]

Atom gets 1 big jump every 2 years rather than smaller ones every year.

IIRC, they finally got funding for yearly releases semi-recently. And clearly MTL was meant as more of a 2022 release, with both Core and Atom cramming in a successor around '23, at least pre-delay.

 

[IntelUser2000]

2023 Meteor Lake= Crestmont
2024 Arrow Lake= Skymont

Sierra Forrest is scheduled for 2024 same as Arrow Lake, so there is a chance it comes with Skymont E-cores rather than Crestmont. And Arrow Lake was planned for Q4 2023 until they went from TSMC 3nm to Intel 20A.

If they are moving to yearly schedules, then the performance gain will be cut, simple as that. Better than not having any of course.

 

[mikk]

10% will be due to speed and IPC combined. MT workload will be a 30% boost at least on 13900K

Where did you get that 30% number?

Iso power?

Edit: I meant "Is there a rumor/leak of that number?"

There is a leak now. In userbench over all cores there is indeed a ~30% boost. 1C-8C is a 5% speedup at best, although we don't know if this 0000 sample is running with the intended final clock speeds.

UserBenchmark: Intel 0000 vs Core i9-12900K

 

[JoeRambo]

Interesting, 32% MT is a substantial gain for 8 extra cores and 5-10% more IPC. A thing to note is that while clocks are unknown, memory is substantially slower on RPL. Still 5-10% "total SP perf ala AMD's 15%" is where I expect RPL to land.

 

[dullard]

Interesting, 32% MT is a substantial gain for 8 extra cores and 5-10% more IPC. A thing to note is that while clocks are unknown, memory is substantially slower on RPL. Still 5-10% "total SP perf ala AMD's 15%" is where I expect RPL to land.

I don't think 32% MT gains is that far off. There are 50% more cores with this chip. Now, the added E-cores are only roughly half as powerful as the P-cores, so you should expect roughly a 25% gain. Add in a few percent for IPC gains from the added cache and 32% seems exactly like what someone should expect.

I don't know why this Raptor Lake chip was running DDR5-4800 instead of DDR5-5600 though.

 

[JoeRambo]

I don't know why this Raptor Lake chip was running DDR5-4800 instead of DDR5-5600 though.

Not only that, it was underperforming vs 12900K running same speed mem.

 

[mikk]

Raichu believes 2300+ ST points in Geekbench might be possible.

https://twitter.com/i/web/status/1532439497757331456

 

[biostud]

AVX512 yes or no on RPL?

 

[JoeRambo]

AVX512 yes or no on RPL?

Nope, small cores do not support it and Intel has disabled it on later production ADL chips. It is counter productive as well, as V/F curve has to take into account AVX512 workloads and has to be worse than it can without AVX512.

 

[jpiniero]

AVX512 yes or no on RPL?

Unlikely. They might even take it out physically but that is also unlikely.

 

[biostud]

So, Intel invents AVX512 and promotes it as the holy grail, then disables it from its chips, and AMD start implementing it from Zen4.

Does intel not believe it to be relevant for desktop?

 

[jpiniero]

So, Intel invents AVX512 and promotes it as the holy grail, then disables it from its chips, and AMD start implementing it from Zen4.

Does intel not believe it to be relevant for desktop?

Not really enough time to come up with a proper solution.

 

[Thala]

I don't think 32% MT gains is that far off. There are 50% more cores with this chip. Now, the added E-cores are only roughly half as powerful as the P-cores, so you should expect roughly a 25% gain.

You might want to convince yourself, that we are talking about a theoretical 33% performance gain, when adding 8 more E-cores without considering any IPC gains.

 

[dullard]

You might want to convince yourself, that we are talking about a theoretical 33% performance gain, when adding 8 more E-cores without considering any IPC gains.

I am sorry, but I do not understand what point you are trying to make. Could you please clarify? Your post about "without considering any IPC gains" really confuses me considering that the line you specifically edited out of my post was "Add in a few percent for IPC gains from the added cache".

 

[Thala]

I am sorry, but I do not understand what point you are trying to make. Could you please clarify? Your post about "without considering any IPC gains" really confuses me considering that the line you specifically edited out of my post was "Add in a few percent for IPC gains from the added cache".

You made the argument, that the performance gain by adding 8 E-cores would be 25%. You then added some additional gain due to IPC increase. My point was, that the theoretical performance gain is already 33% (and not 25%) without taking further IPC gains into consideration.

 

[dullard]

You made the argument, that the performance gain by adding 8 E-cores would be 25%. You then added some additional gain due to IPC increase. My point was, that the theoretical performance gain is already 33% (and not 25%) without taking further IPC gains into consideration.

Thanks, now I see the point you were trying to make. Your post is basically saying:

• Theoretical Raptor Lake gain over Alder Lake = (8 P + 16 E) / (8 P + 8 E)
• Assume performance: 2 E ~= 1 P
• Thus, theoretical gain = (8 P + ~8 P) / (8 P + ~ 4 P) = (~16 P) / (~12 P) = ~1.333
• Thus, a 33% gain even before IPC gains

What your math leaves out is that given the same power constraints, each of Raptor Lake's 24 cores gets less power than each of the Alder Lake's 16 cores. Thus, your math doesn't actually work if you fix the processor at a given power level.

Now we have to get into a bunch of assumptions. How will Intel distribute the same power limitation over more cores? Will the E cores stick with the same power and the P cores get less? Will the P cores stick with the same power and the E cores get less? Something in between?

• Assume the E cores will keep the same power level. Thus, each P cores will go from power in the mid 20s to the lower 20s in watts at turbo (assuming all cores actively performing calculations). That drops the P cores performance down by roughly 6%. Then the Raptor Lake gets only a 29.3% gain.
• Assume the P cores will keep the same power level. Thus, each E cores will lose half the power since there are twice as many. That drops each of the E cores performance down by roughly 55%. Then the Raptor Lake gets only a 3.3% gain. Clearly that is a bad assumption. Why double the E cores and then cripple the E cores by giving them half power?
• Assume something in between. Thus the P cores each lose ~2% performance and the E cores each lose ~10%. End result is Raptor lake is 25% more performance than Alder Lake at the same power.
• Note: all % drops are estimated from here: https://i0.wp.com/chipsandcheese.com/wp-content/uploads/2022/01/image-16-1.png?ssl=1 and this will be very workload dependent.
• Ultimately each assumption effects the 2 E ~= 1 P rough approximation.

Clearly, I don't know how Intel will distribute the power to each core differently (i.e. what frequency each will have). Thus, I did the simple in-between assumption and posted 25% gains (before IPC). I should have been more detailed in my post above.