RAM RAID??

cirthix

Diamond Member
Aug 28, 2004
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If you have two sticks of ddr, one A and one B (A and B are of equal size). Lets assume the fsb runs at C mhz. Any data to be loaded to ram would be D. Any data written to A is also written to B. Now offset dimm B acess by a quarter of a clock such that instead of A and B being read/written to twice a clock cycle, A would be read from, then B, then A, then B, so on and so on. This would increase any latency by a quarter of a clock cycle, but it would double the effective FREQUENCY of the 'ram raid', making your old 1600 (200mhz) able to work clock for clock with a 3200+ (or other 200fsb cpu, like the newer p4s and the a64s) with a little latency added. This idea greatly differs from dual channel because of a few things. Both 'ram raid' and dual channel ram double the bandwidth, but 'ram raid' doubles frequency while dual channel doubles bit width. 'Ram raid' halves memory capacity, while dual channel does not affect it. Dual channel does not add latency to the ram read/writes while 'ram raid' does. Dual channel does not require identically sized dimms, 'ram raid does'. Dual channel greatly affects overclockability by making the chipset work harder, limiting fsb. 'Ram raid would greatly help overclocking because the memory would be effectively doubled. I think the idea would be good overall, but would make using it more expensive ( you have to buy 2x the ram!!, but you get 2x the speed) but it is worth it because 512megs of pc4400 (cl3)can easily cost you 150 usd in one dimm, while you can get 2*512s of lower ram (2700 or 3200) for cheaper, with added latency (it would still be lower even if it is cl2.5 ram because it would end up being cl2.75, yet at pc6400 or 5400. seems like an impressive performance boost for a cheaper product!!! the idea could be scalabel to mor than 2 dimms, but that wold make for some pretty complex clcok generators
 

Matthias99

Diamond Member
Oct 7, 2003
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Originally posted by: cirthix
If you have two sticks of ddr, one A and one B (A and B are of equal size). Lets assume the fsb runs at C mhz. Any data to be loaded to ram would be D. Any data written to A is also written to B.

Okay, you've got mirrored memory.

Now offset dimm B acess by a quarter of a clock such that instead of A and B being read/written to twice a clock cycle, A would be read from, then B, then A, then B, so on and so on. This would increase any latency by a quarter of a clock cycle, but it would double the effective FREQUENCY of the 'ram raid', making your old 1600 (200mhz) able to work clock for clock with a 3200+ (or other 200fsb cpu, like the newer p4s and the a64s) with a little latency added.

But only when doing reads.

This idea greatly differs from dual channel because of a few things. Both 'ram raid' and dual channel ram double the bandwidth, but 'ram raid' doubles frequency while dual channel doubles bit width. 'Ram raid' halves memory capacity, while dual channel does not affect it. Dual channel does not add latency to the ram read/writes while 'ram raid' does.

Uh, that would kill performance in a lot of situations. Especially when writing, because then you effectively halve the bandwidth/speed with mirroring.

Dual channel does not require identically sized dimms, 'ram raid does'. Dual channel greatly affects overclockability by making the chipset work harder, limiting fsb. 'Ram raid would greatly help overclocking because the memory would be effectively doubled.

How is the chipset not 'working harder' with your solution? It's still spreading reads and writes over two memory modules at the same time, just doing it in a different way. Sure, if you run 2xDDR200 it will be easier on the chipset than running dual-channel DDR400 -- but it'll be slower than even single-channel DDR400!

I think the idea would be good overall, but would make using it more expensive ( you have to buy 2x the ram!!, but you get 2x the speed) but it is worth it because 512megs of pc4400 (cl3)can easily cost you 150 usd in one dimm, while you can get 2*512s of lower ram (2700 or 3200) for cheaper, with added latency (it would still be lower even if it is cl2.5 ram because it would end up being cl2.75, yet at pc6400 or 5400. seems like an impressive performance boost for a cheaper product!!! the idea could be scalabel to mor than 2 dimms, but that wold make for some pretty complex clcok generators

It suffers from the same problems that RAID1 does -- mostly that write performance is no better (and is often *worse*) than a single disk, as well as doubling your price/MB. For certain kinds of applications it might make sense, but from a general computing perspective, it's almost always going to be better to have more memory than to double your effective read frequency.
 

Shalmanese

Platinum Member
Sep 29, 2000
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I think he's referring to RAID 0, not RAID 1. Are you sure dual channel doubles bit width? The major problem is that doubling the memory bandwidth actually does very little in terms of real world performance, maybe 3 - 5% in typical use and 10 - 20% maxium. Theres simply not that many applications which require a large memory bandwidth. For the engineering problems it presents, its not a feasible solution.
 

itachi

Senior member
Aug 17, 2004
390
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0
If you have two sticks of ddr, one A and one B (A and B are of equal size). Lets assume the fsb runs at C mhz. Any data to be loaded to ram would be D. Any data written to A is also written to B. Now offset dimm B acess by a quarter of a clock such that instead of A and B being read/written to twice a clock cycle, A would be read from, then B, then A, then B, so on and so on. This would increase any latency by a quarter of a clock cycle, but it would double the effective FREQUENCY of the 'ram raid', making your old 1600 (200mhz) able to work clock for clock with a 3200+ (or other 200fsb cpu, like the newer p4s and the a64s) with a little latency added.
doesn't make sense to put the 2 clocks out of sync. by doing so you're increasing the latency needlessly.

not a bad idea.. but you need to become more familiar with how raid works and how dual-channel memory works. the only processor that might benefit from such technology would be the p4.. the p4 communicates with the mct fast enough to see any performance boost from running it in a raid configuration. athlon xp, on the other hand, wouldn't benefit from this at all.. the bus is bidirectional so it can read/write in the same clock cycle.. but not both at the same time. dual-channel fits it best.

I think he's referring to RAID 0, not RAID 1. Are you sure dual channel doubles bit width? The major problem is that doubling the memory bandwidth actually does very little in terms of real world performance, maybe 3 - 5% in typical use and 10 - 20% maxium. Theres simply not that many applications which require a large memory bandwidth. For the engineering problems it presents, its not a feasible solution.
he's talking about raid 1.. i think.. either that or he's talking about raid 0+1.. but using 2 sticks it's impossible.. dual channel doesn't double the bit width, that's only the way that marketing describes it.. running 2 sticks in raid 0 would double the bit width.
 

glugglug

Diamond Member
Jun 9, 2002
5,340
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Dual channel IS essentially running RAM in RAID 0, with a stripe size of 64 bytes. Doubling the bandwidth is pretty much the whole point of it.
 

TuxDave

Lifer
Oct 8, 2002
10,571
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Originally posted by: glugglug
Dual channel IS essentially running RAM in RAID 0, with a stripe size of 64 bytes. Doubling the bandwidth is pretty much the whole point of it.

That's what I was thinking..... isn't this idea the same as running your ram as dual channels?
 

Matthias99

Diamond Member
Oct 7, 2003
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Originally posted by: TuxDave
Originally posted by: glugglug
Dual channel IS essentially running RAM in RAID 0, with a stripe size of 64 bytes. Doubling the bandwidth is pretty much the whole point of it.

That's what I was thinking..... isn't this idea the same as running your ram as dual channels?

The OP's idea is to run your RAM in "RAID1" (essentially), as opposed to the "RAID0" of normal dual-channel operation. While I've heard of embedded systems that use mirrored ECC RAM configurations for stability purposes (so that if you take a multibit error on one stick, you can recover the data from the second copy), it certainly won't perform better than regular dual-channel memory, since you have to write each piece of data twice (once to each mirrored copy). Interesting, maybe, for 100% uptime servers, but not for most systems, since RAM is so much more reliable than other components like hard drives.

Edit: I suppose that, as with RAID1 hard drive configurations, there could be situations where this would outperform 'RAID0' dual channel memory. However, it would have to be an application that was almost ENTIRELY read-only, and was heavily constrained by memory bandwidth. Maybe if you ran a read-only database off of a RAMdrive?
 

TuxDave

Lifer
Oct 8, 2002
10,571
3
71
Hmm.. ok, interesting. So instead of the shifting the clock by a quarter cycle just have the ability to read two addresses in one read cycle and have it read one from each ram?
 

imported_whatever

Platinum Member
Jul 9, 2004
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it is called interleave iirc, it had been done. many old mobos have an option to let you do that (back with edo or fpm)
 

Sahakiel

Golden Member
Oct 19, 2001
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DDR reads from two memory banks in one clock cycle. Bank 0 sends data on the rising edge and Bank 1 sends data on the falling edge.
DDR-II output is clocked twice as fast as the memory. Bank 0 sends data on the rising edge and Bank 1 sends data on the falling edge. Bank 2 sends data on the rising edge and Bank 3 sends data on the falling edge for a total of four banks read back to back in one clock cycle. That's also why DDR-II latencies are higher than DDR. It's a matter of reference points.