RAM matching FSB question

[shuan24]

I am building a box with a XP 3200+ Barton that supports 400Mhz FSB. Obviously the choice of RAM should be PC3200 correct? Since it is DDR400 and it matches the FSB clock evenly.

But if PC6400 existed today (which it might), wouldn't DDR800 be better as far as timing matching goes?

 

[Matthias99]

Your "400MHz" FSB is a 200MHz FSB using DDR RAM (likewise, Intel's "800Mhz" FSB is a quad-pumped 200Mhz FSB). If you really had a 400MHz FSB, you would need DDR800 (or, more likely, DDR2-800, since DDR doesn't go that fast). "DDR400/PC3200" RAM runs at 200Mhz real clock, but transfers twice per clock cycle (hence Dual Data Rate, or DDR). DDR800 on a 200Mhz FSB would be wasting every other clock cycle of the RAM.

 

[shuan24]

Ok so the Athlon XP advertising that it supports 400FSB is actually 2x 200Mhz FSB, correct? I understand how/what DDR clocks, I was just curious as to what the real FSB on motherboards/processors were.

 

[Matthias99]

There are no motherboards or CPUs with higher than a 200Mhz (stock) FSB (real clock speed). PC3200 is the highest JEDEC spec for RAM, so it doesn't make a whole lot of sense to build them higher than that at stock.

Basically, calling it a "400Mhz" FSB is a misnomer. It's a 200Mhz FSB, which uses DDR400/PC3200 RAM (at 200Mhz real clock, 400Mhz effective clock).

 

[itachi]

correct me if i'm wrong.. but considering that the modules output at every edge of the clock cycle, the output frequency is more accuractely described by 400 mhz with a 200 mhz internal reference for the modules only. suppose that a cache miss occurs for a block of size 64 kb. when the request goes out to the controller and the module initiates the transfer, the data will begin to load into the L2 cache.. if the modules transferred quad word at a time every [200mhz] clock cycle, then i'd agree with that statement.. but it doesnt, transfers are done with double words at every edge of the clock signal. relative to the cpus core clock speed, data will be transferring at a rate of 400 mhz.. and as far as i know, cpus have no necessity for the sstl that ddr utilizes in place of ttl.. given that, the cpu wouldn't be loading with reference to a 200 mhz clock but a 400.
i know that data does have to go into the memory modules.. and that data can't just magically appear at the other end of the pins without the command being sent down the command bus.. both of which are governed by a single edge, so i can't say indefinitely that the fsb is 400.. but just as well, i don't think you can say indefinitely that the fsb is 200.

am i missing something here..?

 

[Dough1397]

p4ee 1066 fsb which is really a 266 fsb quad pumped (266 * 4) it does go higher than 200

 

[Peter]

Originally posted by: shuan24
Ok so the Athlon XP advertising that it supports 400FSB is actually 2x 200Mhz FSB, correct? I understand how/what DDR clocks, I was just curious as to what the real FSB on motherboards/processors were.

The "400FSB" is actually 200 MHz DDR. So is PC3200 RAM. Complaints about the silly inflated numbers go to marketing, thank you.

 

[TuxDave]

Originally posted by: itachi
correct me if i'm wrong.. but considering that the modules output at every edge of the clock cycle, the output frequency is more accuractely described by 400 mhz with a 200 mhz internal reference for the modules only. suppose that a cache miss occurs for a block of size 64 kb. when the request goes out to the controller and the module initiates the transfer, the data will begin to load into the L2 cache.. if the modules transferred quad word at a time every [200mhz] clock cycle, then i'd agree with that statement.. but it doesnt, transfers are done with double words at every edge of the clock signal. relative to the cpus core clock speed, data will be transferring at a rate of 400 mhz.. and as far as i know, cpus have no necessity for the sstl that ddr utilizes in place of ttl.. given that, the cpu wouldn't be loading with reference to a 200 mhz clock but a 400.
i know that data does have to go into the memory modules.. and that data can't just magically appear at the other end of the pins without the command being sent down the command bus.. both of which are governed by a single edge, so i can't say indefinitely that the fsb is 400.. but just as well, i don't think you can say indefinitely that the fsb is 200.

am i missing something here..?

How about a 200MHz clock with 400Mbps data rate with data arriving on every clock edge.

 

[Peter]

The point why 200 MHz DDR does not equal 400 MHz is that only the data transfers are speed-doubled. Command, addressing and all the other housekeeping is not. E.g. where PC133 SDR would take 12+8 cycles for a full address transmission and a cacheline of data (eight quadwords), PC2100 DDR (still at 133 MHz) would take 12+(8/2) ... which is 16 cycles instead of 20, far from actually doubled speed.

(Full-address accesses are the worst case. Most of the traffic is typically CAS-only, with a drastically lower number of lead cycles.)