Quick question on byte-addressable memory granularity

[duragezic]

Part of this assignment I have is: given a 32-bit address, determine the size of the cache, size of a line, etc.

In a previous class, we did quite a bit of these problems, except that the word-size was equal to the address length (32 bits / 4 bytes). But this particular problem has the word size being 1 byte. So are the 2 least significant bits in the address still 0, even with the word-size being 1 byte? Because for every cache address problem we had with 4 byte words, the two right-most bits in the address were always zero (aligned on the boundary or whatever?), thus the word select field in the address was actually 2 bits less than it said. But I'm not sure if this is till the case with 1 byte words. Any idea?

 

[mundane]

Sounds like a software question.

 

[her209]

There's not enough information to solve this problem.

 

[her209]

Originally posted by: mundane
Sounds like a software question.

No, it belongs in Highly Technical.

 

[duragezic]

Well I know how to calculate the required stuff given the 32-bit address, but I don't know if I should subtract two bits from the right-most/word select field in the address, since the problems I've done in the past have had these two LSB be zero to align it right. But with the word size being just 1 byte I'm not sure if that's still the case.

So given a 32-bit address of:

tag----|-index---|--pos (what I call the word-select)--|
20 bits|-8 bits---|----4 bits--------|

My professor helped me with other aspects of this, but didn't specifically answer this question.. he simply gave me the word-size as 1 byte. For my other class, I would use 2^(pos bits - 2) to calculate the number of words in a cache block, but since the word size is smaller I'm not sure if I still use that or 2^(pos bits).


And I'm not sure how this is software? It requires a pencil and the piece of paper. It's homework as you surely can tell, but I'm just trying to get clarification on this issue... I can do the calculations easily (though some of them are indetermine from given info).

 

[Special K]

Originally posted by: duragezic
Part of this assignment I have is: given a 32-bit address, determine the size of the cache, size of a line, etc.

In a previous class, we did quite a bit of these problems, except that the word-size was equal to the address length (32 bits / 4 bytes). But this particular problem has the word size being 1 byte. So are the 2 least significant bits in the address still 0, even with the word-size being 1 byte? Because for every cache address problem we had with 4 byte words, the two right-most bits in the address were always zero (aligned on the boundary or whatever?), thus the word select field in the address was actually 2 bits less than it said. But I'm not sure if this is till the case with 1 byte words. Any idea?

First of all, are you using the terms "word" and "cache line" interchangeably?

In every cache problem I've solved, the least significant bits are the word/byte offsets. If a word (cache line) is only 1 byte long, you should only need 1 bit for the offset.

 

[KLin]

Definitely a do your own homework response is in order here.