Quick question: how does a quad pumped bus work?

[Darien]

So with DDR you use the rising/falling edge of a clock signal. That I can understand.

But a quad pumped bus? How do you get get twice as much data pushed through compared to DDR?

Thanks.

 

[Darien]

bump

 

[n7]

Try Here

 

[deftron]

pumped bus x 4

 

[ElFenix]

probably by using different voltage levels, but then i'm not an engineer.

i always suspected that intel's rdram fiasco had to do with that quad pumped bus, as rdram employs one as well.

 

[Darien]

Originally posted by: n7
Try Here

This place gets way more traffic

 

[Darien]

ttt

 

[amol]

Originally posted by: Darien

Originally posted by: n7
Try Here

This place gets way more traffic

that's one of the worst reasons ever

and yet, no one has answered your question yet

would have been answered in HT

 

[canadageek]

DDR(double data rate) sends two bits of information per clock cycle
AMD Athlon XP fsb is "double pumped" in that it sends two bits/cycle.its real speed=200Mhz fsb, but it's "effective" speed is 400Mhz
quad-pumped, sends four bits per cycle, so the 200Mhz becomes effectively 800

 

[JulesMaximus]

Welcome, this is Off Topic.

 

[aplefka]

Originally posted by: Darien

Originally posted by: n7
Try Here

This place gets way more traffic

Very true, however the people that DO frequent HT know what they're talking about and you'll get a much more thorough and overall better answer there than here, even if you get a faster response here.

 

[cavemanmoron]

uh it has 4 air bags,and when the bus stops to let people on/off the bus
the air bags deflate,so the people can get onto the bus easier.

 

[imported_FishTaco]

EDIT: new link, old link was to quad rate SRAM, this link is to DDR-II which is what I think you're asking about.

http://www.lostcircuits.com/memory/ddrii/2.shtml

basicially, the I/O buffer runs at twice the memory core rate, data is transfered on the rising and falling edges of the doubled core rate, hence 4 possible transfers per core clock cycle.

 

[aplefka]

Originally posted by: cavemanmoron
uh it has 4 air bags,and when the bus stops to let people on/off the bus
the air bags deflate,so the people can get onto the bus easier.

Way to live up to your name.

 

[cavemanmoron]

Originally posted by: aplefka

Originally posted by: cavemanmoron
uh it has 4 air bags,and when the bus stops to let people on/off the bus
the air bags deflate,so the people can get onto the bus easier.

Way to live up to your name.

Topic Title: Quick question: how does a quad pumped bus work?

Glad I could help in OFF TOPIC.

 

[Darien]

Originally posted by: FishTaco
EDIT: new link, old link was to quad rate SRAM, this link is to DDR-II which is what I think you're asking about.

http://www.lostcircuits.com/memory/ddrii/2.shtml

basicially, the I/O buffer runs at twice the memory core rate, data is transfered on the rising and falling edges of the doubled core rate, hence 4 possible transfers per core clock cycle.

Thanks! :beer:

ATOT pulls through again!

 

[Toastedlightly]

Hey guys, you seen those Danika pics?!2121omglolsteam

 

[Darien]

Hahaha, I was wondering when a reference to Danica was going to show up. Ah, the nef fest on a serious question continues. Next I'll see someone post about how they're in agony for stepping on an ant.