Quick question for the EEs

[duragezic]

In lab we had to implement a 8-bit adder. I chose to write the adder module in Verilog, simply using two 8-bit inputs and the sum as a 9-bit output. Then I had to write another module to convert the result into two hex digits to be displayed on a seven-segment display. In the report I'm asked what kind of adder I used. Well I sort of have an idea about a couple different types, but it's not that I actually coded the addition. I didn't have to worry about Cin/Cout, only used the line Sum = x + y;... So I looked up information on the Verilog operators but I couldnt see that they defined the addition operator as a certain type of adder. Any ideas?

 

[CanOWorms]

For FPGAs, I think that it would be a ripple if you just used +.

 

[RaynorWolfcastle]

Originally posted by: CanOWorms
For FPGAs, I think that it would be a ripple if you just used +.

Yeah, I would say ripple as well

 

[JohnCU]

aren't they all ripple?

 

[duragezic]

Hmm, ripple it is. I've been searching high and low for any sort of explanation, but I guess I just gotta make something up about it being ripple-carry.

 

[CanOWorms]

Originally posted by: duragezic
Hmm, ripple it is. I've been searching high and low for any sort of explanation, but I guess I just gotta make something up about it being ripple-carry.

Well, in the use of FPGAs, just using '+' would be a ripple carry because a ripple-carry is unusually faster than other adders because of the FPGA architecture (unless you're going for a very large adder) since it's given for free and optimized.

 

[JetBlack69]

Originally posted by: JohnCU
aren't they all ripple?

There are also carry-lookahead adders, but I don't know if FPGAs implement those.

 

[huesmann]

Black Adders!

 

[Deeko]

carry lookahead is fun.

I'm not familiar with verilog...is it strictly behavioral architectures? That's too easy

<- just wrote a structural design for a single cycle MIPS datapath in Symphony last night.

 

[TuxDave]

Originally posted by: Deeko
carry lookahead is fun.

I'm not familiar with verilog...is it strictly behavioral architectures? That's too easy

<- just wrote a structural design for a single cycle MIPS datapath in Symphony last night.

It's all about the Ling's Adder yo... (different version of a traditional p-g carry lookahead adder)