quick computing question

[aceman817]

i couldn't find another forum to post this under so here goes. one of my professors assigned as a question the following:

Describe a parallel architecture that uses pipeline processing. Draw the diagram for 3 and 5 sub-cycles of the instruction cycle

so far i put that a parallel architecture that uses pipeline processing consists of multiple processors arranged in tandem where each one contributes part of an overall computation. what would the diagram look like for 3 and 5 sub cycles? i searched around the net and only confused myself more. maybe someone here has a thought on what the diagrams should look like.

Thanks,
AL

 

[itachi]

cycle 1, instruction 1 begins.. cycle 2, instruction 2 begins.. etc..
given that at cycle n, instr n is at stage 1..
"at clock cycle 3, where is instruction 1 and 2 in the pipeline?"
"at clock cycle 5, where is instruction 1, 2, 3, and 4 in the pipeline?"