Question Questions about CPU/Motherboard relationships with DDR SDRAM

Jeonghwan Park

Junior Member
Mar 31, 2023
My prior knowledge
1. Memory controller in CPU can control 2 DIMMs. (64bits per dimm. so, 64 bits x 2 = 128 bits bandwidth)
2. Usually, there are two memory controllers within the CPU.
3. For dual rank memory, it looks like a single DIMM, but it actually has two DIMMs. (Faster than single rank memory because it has 128bit bandwidth)

Question 1
Does it work if all four memory slots on the motherboard are equipped with dual rank memory?
In my opinion, two memory controllers in the CPU can control a total of four DIMMs (2 dimms per controller. so, 4 rank = 256 bits bandwidth), So I think put dual rank in 4 memory slots, it won't work because it's 8 ranks (512bit bandwidth).

Question 2
As far as I know, if dual rank memory is installed in the same channel (A1, A2), it is no problem to working.
In my opinion, one memory controller has 128 bits bandwidth (2 rank), So if both the A1 and A2 slots controlled by a single memory controller are equipped with dual rank memory, it won't work because there are a total of four banks.

Question 3
What is mean of "Maximum DIMMs" in manufacturer's motherboard specification?
Only the number of memory slots? Or, Specification for a separate chipset(I'm not sure it is exists) between the CPU memory controller and memory slot?


Golden Member
Jun 6, 2013
Your math is off because your concepts are wrong.

On consumer platforms, your total Bus Width is never higher than 64/128 Bits (Or 72/144 Bits if ECC, up to DDR4 generation. DDR5 is different). Memory Controller can be either a single 128 Bits one or two 64 Bits ones, for this that doesn't matter (Does anyone remembers AM3 Phenom II Ganged/Unganged modes?). You sum Bus Width as you add Channels because they are accessed simultaneously, but only a single Rank is active at a given time in the Channel, so it is still 64 Bits per Channel regardless of how many Ranks you have.
You can usually get slighty more performance out of a Dual Rank DIMMs (Or two Single Rank DIMMs, which are equivalent) due to Rank Interleaving techniques, which is when one Rank is doing internal, non-Bus actions like refreshing DRAM contents, the other Rank uses the Channel, so you get more effective Bandwidth out of the possible maximum theorical. Here is a benchmark.
If you google around, it wouldn't take you too long to find 128 GiB DDR4 configurations that are made out of 4 Dual Rank DIMMs. 4 Ranks per 64/72 Channel as 2 Dual Rank DIMMs per Channel is standard. Enough proof that it works.
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