Question on the upcoming Core i5

[phillyman36]

Hey I know the i7 from what ive read is about a 7% ish improvement over penyrn with the biggest difference in media encoding being alot more. My question is the upcoming Core i5. Does any one know what the difference between the i5 and Penryn will be? Are any of you going to switch your penyrn for a i5? I read the i7 has qpi (intergrated memory controller and the i5 has Dmi. What does this mean?

Thanks for any info. Im just trying to understand what differences and benefits between each other. Please forgive me if i got any info wrong.

 

[jones377]

i5 will integrate the last remaining item from the traditional northbridge, the 16x pci-e controller. So because of that, it doesn't need QPI because the only other chip will be the southbridge and compared to the northbridge, the southbridge doesn't need that much bandwidth. The only downside to this solution is with SLI/Crossfire as they would have to split up the integrated pci-e into two 8-pcie lanes. But if you don't care about SLI/crossfire then it won't matter to you. The other downside to i5 will be only 2 channel in the memory controller compared to 3 on the i7.

i7: 3 channel DDR3, QPI, 32x PCI-E on the northbridge
i5: 2 channel DDR3, 16x PCI-e integrated

 

[VirtualLarry]

Would it be correct to assume that the i5 will never see a server variant, due to lack of QPI bus?

 

[Idontcare]

Is it accurate to say QPI is absent from i5? Or is it more accurate to say QPI is present but exclusive to use internal to the chip itself? Isn't the Nehalem chip in i5 still communicating with the integrated NB components via QPI?

 

[ilkhan]

As IDC said, QPI *IS* used on the i5's. It still connects the CPU to the northbridge, but as both processors are on one die, you never SEE QPI. DMI is the current NB<->SB link, and thats exactly it's function with i5. (look at the clarkdale/arrandale layout, the memory controller isn't on the same die as the processor, QPI connects them.)

i5 will be a little slower than i7, but not by much. The memory bandwidth with i7 is HUGE, and is overkill for most things. The hex-core, faster stock speeds (and likely only extreme SKU), x16/x16 SLI, and dual-socket capabilities will be the biggest differentiators.

AFAIK most single socket servers will be LGA1156, while two socket servers will be LGA1366. That just seems needlessly confusing to me, but thats whats on the roadmaps IIRC.

 

[VirtualLarry]

Originally posted by: ilkhan
As IDC said, QPI *IS* used on the i5's. It still connects the CPU to the northbridge, but as both processors are on one die, you never SEE QPI.

Considering how much of the die is taken up by QPI, according to the die shots of the i7, is that wise for Intel to use QPI internally? Wouldn't some sort of custom bus be more die-efficient? Or is it an engineering tradeoff, eg. they already spent the R&D creating QPI, why not use it, even as an on-die bus.

 

[Idontcare]

Originally posted by: VirtualLarry

Originally posted by: ilkhan
As IDC said, QPI *IS* used on the i5's. It still connects the CPU to the northbridge, but as both processors are on one die, you never SEE QPI.

Considering how much of the die is taken up by QPI, according to the die shots of the i7, is that wise for Intel to use QPI internally? Wouldn't some sort of custom bus be more die-efficient? Or is it an engineering tradeoff, eg. they already spent the R&D creating QPI, why not use it, even as an on-die bus.

Well if they eliminate QPI then they have to replace it's function with something else that functions in a way that serves the same function...a black line drawn between a box labeled PCIe and another box labeled Core only works in powerpoint...and that would take time/money as well.

Since they knew this, of course, when designing QPI for Nehalem one would be compelled to assume they factored in the i5 situation while optimizing what QPI is and does.

 

[vnvnvn2000]

The Core i5 is a Lynnfield processor which is itself based on the Nehalem Intel Core microarchitecture. It features an integrated memory controller supporting 2-channel DDR3, hyper-threading technology (which means that four cores translates into processing capacity for eight threads), features 8MB of Intel Smart Cache, and supports Turbo Boost technology and an integrated PCI-Express graphics controller. The socket for this chip differs from the LGA1366 used by the Core i7 (Bloomfield). So what?s the difference between the Core i5 and Core i7? Core i5 CPUs don?t make use of Intel?s QuickPath Interconnect.

 

[IntelUser2000]

To the OP: Where did you get the number 7%? The total average performance increase of non-synthetic applications came out to be 20%. You'd be right for game-only.

PCI-Express being on CPU is actually an advantage over current Nehalem in single GPU configurations because latency will be reduced. Only way to explain why i7 excels at low resolution single GPU/high resolution multi-GPU but fails to bring much at high resolution single GPU setups.

I'd bet Lynnfield(quad core with no IGP) will be faster per clock than Bloomfield(current i7) in high res single GPU set ups because of that.

Considering how much of the die is taken up by QPI, according to the die shots of the i7, is that wise for Intel to use QPI internally? Wouldn't some sort of custom bus be more die-efficient? Or is it an engineering tradeoff, eg. they already spent the R&D creating QPI, why not use it, even as an on-die bus.

It'd probably be more efficient, but not in the extra engineering required. QPI is designed to be very scalable and it would be cheaper for them to stick to an established standard.

It looks like Lynnfield(the quad core) won't use QPI at all. Only the Havendale/Arrandale is planned to use QPI for internal communications. It would make sense because it would be faster performance wise to not go through the QPI for memory access but on the same die. On dual-die IGP implementations though, the only way to connect the two is by using QPI.

 

[ilkhan]

Originally posted by: vnvnvn2000
The Core i5 is a Lynnfield processor which is itself based on the Nehalem Intel Core microarchitecture. It features an integrated memory controller supporting 2-channel DDR3, hyper-threading technology (which means that four cores translates into processing capacity for eight threads), features 8MB of Intel Smart Cache, and supports Turbo Boost technology and an integrated PCI-Express graphics controller. The socket for this chip differs from the LGA1366 used by the Core i7 (Bloomfield). So what?s the difference between the Core i5 and Core i7? Core i5 CPUs don?t make use of Intel?s QuickPath Interconnect.

i7 doesnt have the PCI-E controller
i7 has a third memory channel
i7 connects to an external northbridge

i5 is a great setup for single socket configs (with x8/x8). Everything about i7 is setup for two-socket operations (and x16/x16).

Originally posted by: IntelUser2000It looks like Lynnfield(the quad core) won't use QPI at all. Only the Havendale/Arrandale is planned to use QPI for internal communications. It would make sense because it would be faster performance wise to not go through the QPI for memory access but on the same die. On dual-die IGP implementations though, the only way to connect the two is by using QPI.

From what I can tell QPI is used even on the same die to connect to the memory controller. But I don't have any extra info on that.

 

[phillyman36]

So basically if i only run one video card(no sli ever) core i5 maybe the better option rather than i7?