question for the gurus

[morgash]

been wonderin about some things and need some answers if anyone has em

1. Is the L1/L2/L3 cache on a law of diminishing returns as its size goes up as far as performance is concerned and if not why are the cache sizes not 512mb-1gb thereby allowing the riddance of sytem RAM and the whole FSB bottleneck.

2. Single channel channel RAM is 64-bits wide while dual channel is 128 bits wide. High end video card RAM is 256 bits wide, so are they running quad channel? if so then two questions come up.
a. since on videocards with 128-bit memory interfaces at a certain speed there is no performance gain afterwards because of the bottleneck at the 128bit, will this be the case eventually with DDR and will we see tri and quad channel RAM in the future?
b. and if the question above is true, does this mean that Sony/Rambus's new XDR memory for the PS3 runs on an even higher memory bitrate? its clocked somewhere around the 3-4 ghz range so i would think that even the mighty 256 bit would have bottlenecked b4 then.

THanks in advance for all answers, might think of more l8r cuz i feel like ive missed something. Hope this is informative to everyone cuz ive been wondering this for a while.

Morgash

 

[morgash]

still need t aknow

 

[ahurtt]

Wrong forum?

 

[smack Down]

L1/L2/L3 is on diminishing returns because the amount of memory that has localitty is small. Let say that your L1 cache has a 5% miss rate. The 5% of memory that was missed is going to be harder for CPU to cache because it is farther away. Like a jump to a new subroutine or loading data that hasn't been used. As the size of a cache increases its speed decreases so you can't make massive caches that are fast. The also eat area.

A) Most likely we will see smaller bus instead of wider ones due to costs. A wider bus is harder to design for and can't operate at higher frequencies.

B) I don't know about the PS3 but my guess is if RAMBUS is involved then it is higher frequency lower bit rate bus.

 

[Matthias99]

Originally posted by: morgash
been wonderin about some things and need some answers if anyone has em

1. Is the L1/L2/L3 cache on a law of diminishing returns as its size goes up as far as performance is concerned and if not why are the cache sizes not 512mb-1gb thereby allowing the riddance of sytem RAM and the whole FSB bottleneck.

It's not 512MB-1GB because building that much high-speed SRAM would take at least a hundred times as many transistors as today's CPUs use in total. A high-end P4 with 2MB of L2 cache already has at least 2/3 of its transistors used just for cache memory. Having more high-speed cache would improve performance -- but the cost is simply not feasable for a 'normal' PC.

There is *somewhat* of an effect of diminishing returns -- for instance, going from a 16K L1 cache to a 32K cache is a 100% improvement, but then going from 32K to 48K, while having the same increase in transistor count, is only a 50% improvement. Basically, increasing cache sizes is VERY expensive, so it's generally more effective to improve other parts of the system instead.

At this time, the only feasable way (economically) to have more than a few megabytes of RAM is to have it be DRAM. The 'FSB bottleneck' is more effectively addressed by using a memory controller built into the CPU (as on the Athlon64) than trying to massively increase the amount of cache.

2. Single channel channel RAM is 64-bits wide while dual channel is 128 bits wide. High end video card RAM is 256 bits wide, so are they running quad channel?

Yes.

a. since on videocards with 128-bit memory interfaces at a certain speed there is no performance gain afterwards because of the bottleneck at the 128bit, will this be the case eventually with DDR and will we see tri and quad channel RAM in the future?

Well, what really matters is the memory bandwidth (bus width * clockspeed), not the interface width per se. If memory keeps getting faster, they may not need to go to significantly wider buses. If memory doesn't get much faster, buses will get wider so as to increase bandwidth -- at least on the GPU side. CPUs don't need uber-high memory bandwidth quite as much, generally, since at some point the CPU just can't keep up.

Note that multi-CPU Opteron servers use the memory controllers on all the CPUs -- so a 4-way Opteron server effectively has a 512-bit memory bus, just split between the four CPUs. That's one of the reasons that they scale so much better than Xeon MP servers.

b. and if the question above is true, does this mean that Sony/Rambus's new XDR memory for the PS3 runs on an even higher memory bitrate? its clocked somewhere around the 3-4 ghz range so i would think that even the mighty 256 bit would have bottlenecked b4 then.

Sorry, not sure. Very little info has come out so far on the PS3's hardware.