Question about DRAM and PCI and layering

Lvsheng

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Mar 9, 2001
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Some review here mentioned about "Full length PCI card", what is mean by full length and not full length? Then I saw that some board share IRQ. I am wondering that how the OS know which devices interupt it since there are several PCI slots that share the same IRQ. Can anyone please provide a good explaination?

RDRAM Facts

At the above article, Anand said:
Remember that RDRAM is a serial device, so at any given time, you're transferring one bit of data at a time instead of transferring multiple data bits in parallel, which is the case in SDRAM.

I don't understand this. Since RDRAM has 16 bit wide bus (16 traces, right?), and we are only transfering 1 bit at a time, what are those 15 bit remaining bus used for?

Then in i840 chipset, it use 2 channel RDRAM. What is this 2 channel mean? Is it having 2 independant 16 bit bus (32 bit bus in total)? In i850 chipset, we need to install 2 RDRAM together at once right (due to 2 channel RDRAM design)? Why 2 channel will require 2 RDRAM to be install together?

In the same article, Anand said that it uses some mobo eg Abit uses 4 layers PCB design. Is it means that there are even traces inside the board (not on the 2 top surface)? How do manufacturer do that and why having more layer is better as in the case of PC100 SDRAM?


And then back to the SeverSet III HEsl article:

AnandTech ServerSet III article

The author mentioned about 2 way interleaving at PC133 will enable DDR performence. What is this 2 way interleave means? What about 4 way interleave, what it means?

Thank you :D
 

AndyHui

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Hhmm....where to start?

A full length PCI card runs the length of the entire motherboard, and in many cases, runs the entire length of the case....from the metal bracket at the back of the case all the way to the front of the case. Placing connectors in front of the PCI slots may block the slot and prevent full length cards from being inserted.

These days, most PCI cards are &quot;half-length&quot;, in that they do not take up the entire length of the motherboard/case.

Interrupts are used by the Processor, and are not really a function of the Operating System. Sharing of IRQs is part of the PCI specification.

16 traces for an RDRAM device is a poor assumption. RDRAM not only sends data, but it must send controlling signals (Start, Stop, Precharge, Wake, etc) and power as well. One bit is sent in each &quot;bit slot&quot;.....a bus 16-bits wide means that it will send 16-bits of data at a time....ie 2 bytes. Since RDRAM is &quot;DDR&quot;, sending data on both edges of the clock signal, it sends 4 bytes per clock cycle.

In the i840 chipset, a dual channel means that there are 2 separate memory banks that lets RDRAM effectively send double the amound of data, ie a total of 32-bits, or 8 bytes per clock cycle.

Dual channel requires both channels to have RAM present because both banks are multiplexed and accessed at the same time.

More layers on the motherboard result in higher stability as there is less interference and cross talk between the traces. More layers results in a higher cost though.
 

Lvsheng

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Mar 9, 2001
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Thank you AndyHui for your kind reply.

I still have some doubt about the RDRAM. If it send 16 bit at a same time, isn't that it will become parellel? In SDRAM, the RAM send 64 bit at a same time to the chipset via its data bus so this is know as parellel. So assume it has 64 traces for the data bus, SDRAM at any time will make sure each traces will have 1 bit travelling at a time (if it is transfering data).

So for instance, if SDRAM is going to output 8 byte, all its traces will be ocupy as each will send a bit to the controller right? This is known as parellel transmission, right?

But in the case of RDRAM, it only send 1 bit, because it is serial. So take back the same example, if RDRAM want to send 8 byte of data, it has a total of 64 bit to send. But since it is serial it will only send all these bit at the same traces, thus only occupying 1 traces (leaving 15 unuse), is it correct?

I know RDRAM send 16 * 2 bit at each clock cycle, that is what I know from the spec. But it is somehow contradicting with what Anand discuss. Maybe I just misinterpret or I have a wrong concept. In what I have read before, parellel is the kind of transmission that have many buses, and each will transmit data at the same time. Serial transmission in contrase only have 1 bus and it will send bit by bit thru that only avail bus. That is why it is said that serial transmission is poor is performence (remember the serial port and parellel port on the back of your PC?). But this concept seems to be cannot implement in the RDRAM case, which it claims transferring 16 bit at once, that will be same as parellel because there are more than 1 bus transfering data. That is my opinion now (which may be wrong).

So anyone can clarify this?

Yeah one more thing, why we can only send signal on the rising edge and falling edge only?
 

AndyHui

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I think you have the wrong concept regarding serialisation of RDRAM and SDRAM. In RDRAM, serialisation means that it data is moving through a single RDRAM chip at a time, so in this regard it is only one bus. The bus is a single signal that moves from one RDRAM chip to the next all the way to the end until it goes back to the controller.

SDRAM accesses the entire bank, or ALL SDRAM chips on the DIMM at a time. This is why SDRAM is classed as parallel.
 

Tsaico

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Oct 21, 2000
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Well, the other stuff I just learned with you, but the high or low signals is there because despite all that you computer is doing, it is really just a complex series of switches and gates. Computers are digital, not analog... Only the two exremes are considered, the rest is just noise...
 

Lvsheng

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Mar 9, 2001
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Oh... now I understand about the serial and parallel between RDRAM and SDRAM. So in essence, it means that because everytime SDRAM send data out, all 8 devices on the RAM must be used (just like using 8 traces). But in RDRAM it only use 1 device on that RAM to output the data (just like using 1 traces). So this make them appear as parallel and serial. Correct, right?

Errr, but from your last message, why we need to go from one device to another in RDRAM, why don't we just output the data straight away from the device? And that 64 bit in SDRAM make up one bus right? You mention &quot;only one bus&quot;, there is a second bus???

Well anyway thanks for your reply AndyHui, and 1 more thing, how to change the 'junior member' to other words?
 

AndyHui

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Your first point is correct. With regard to the second point, that is due to the design of the entire RDRAM system. The point &quot;one bus&quot; was used to contrast with SDRAM.

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Lvsheng

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Mar 9, 2001
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Tsaico, if you said like that then it means all SDR will always carry a 0 value. Because from what I know prior to DDR, computer only carrying signal at the falling edge. With DDR, they carry the data both at rising and falling edge. So if you mean falling edge is 0 then all those SDR device out there will always carry a 0 value. Isn't that impractical? Or maybe it is me that misinterpret your words? Please provide further explaination about those signal.

Actually I am also doubt with this because computer signal is just on or off, how come we got rising edge and falling edge?

If plot in the graf, the signal should be just a straight horizontal line at 1 or 0. I just simply can't understand how they manage to get a quadratic graf. And I also dunno how those QDR works. How they manage to carry the signal, 2 at rising, 2 at falling edge???
 

AndyHui

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QDR is DDR with double the bus width. 2 x 2 = 4. 4 times the data of the original.

The clock signal is -|_|-|_|....there are two edges of each high...: | Hmm...I can't get a high bar....oh well....you get the idea.

Electrical signalling is not just 1 and 0. There's 0, -1 and 1 as part of the direct electronic voltage.
 

Lvsheng

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Mar 9, 2001
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Errr, sorry I can't get your idea.

-|_|-|_|

Can you please define all the character inside there? Like:

- = xxx | = yyy _ = zzz

Or may be you might use 2 line as well like:
..| (eliminate the dot since i can't type the space, browser won't display)
-| |- (something like this, may be a bit clearer)

Thing just get really more and more complicated. Isn't computer hardware fun to learn? Ha Ha
 

AndyHui

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What I am trying to draw is a square wave.
 

Lvsheng

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Mar 9, 2001
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Wow, you reply very fast, just like sending message in ICQ (Where we have instant reply).
Well, never mind, i will just explore go and find some more info about this when i am free. Can't get what you mean by a square wave. Sometimes, we really need graphics to clearly represent some concept.
 

Lvsheng

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Mar 9, 2001
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Oh yeah, before I go out, I would like to ask what is those shared PCI slot? I always stumble across, master PCI, slave PCI. Those master PCI can do bus master right? And those slave one can't bus master right? What about the share PCI?
 

AndyHui

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There's a difference between shared PCI slots and IRQ sharing.

Shared PCI slots are slots that share the bracket space on the back with either an ISA slot or an AMR/CNR slot.

Master PCI devices as you call them are capable of bus mastering, while &quot;slave devices&quot; cannot.

IRQ sharing simply means that more than one device can use the same IRQ.