There are two ways to reduce the die size of a specific microarchitectural design. You can shrink it, or you can compact it. A shrink is an optical shrink of all of the gates along with the corresponding process chemistry to make this work. Examples of straight shrinks are hard to find nowadays because it's not as easy as it used to be due to the widespread use of OPC (Optical Proximity Correction) and phase-shifted mask techniques that make it very hard to optically shift a design. The last two completely straight shrinks that I can think of at Intel were the P54CQS (120 and 133MHz Pentium) and the P6S (200MHz Pentium Pro). More recently more work has to go into the shrink process so straight shrinks don't occur any more at Intel (at least not any that I can think), nor can I imagine you see them anywhere else nowadays. OPC and phase-shifting make it simply too hard. Besides shrinks were never able to fully take advantage of a process. Usually a new process would add a new feature - like a new metal layer for routing - and these would by necessity be completely ignored by a shrink. In addition the changing wire characteristics, and transistor speeds often changed the speed paths such that the chip would not run as fast as it would have with a partial redesign. Shrinks still occur, but now they are usually ~5% shrinks (as opposed to a full process shrink which would be ~30%).
The other thing, which is how it is normally done nowadays, is a "compaction shrink" (quotes added to deliniate a term that I'm not sure is correct). Northwood was a compaction shrink of Willamette, etc. In this, the whole die is re-layed out and units are moved around. Usually an attempt is made to minimize the amount of changing that occurs (to keep schedule and team size small) so schematics generally remain the same, but changes to circuitry and wiring are made to take better advantage of the new process characteristics. The die size is small than it would be with a shrink, and the circuitry generally runs quite a bit faster.
An example is the Pentium:
P54CQS released March 1994 at 120/133MHz with a die size of 483x525 mils on a 0.35um process.
P54CS released December 1994 at 133/150/166MHz with a die size of 361x392 mils on the same 0.35um process.
Both were derivatives of the P54C design (which was 0.50um) and both used the same identical process. P54CQS (P54CS - Quick Shrink) was essentially an optical 30% shrink. P54CS was a compaction shrink of P54C onto the new process.
