Question about AGP and PCI dividers and what exactly controls them...

[Insane3D]

I am curious about what exactly controls the AGP and PCI divisors in current motherboards. I have always been under the impression that the clock generator controls these frequencies, and the bios enables the different ratios that the clock gen supports. I have been in a debate about the new KT266A based motherboard, the 8KHA+. I have this board, and I was excited to see that the clock generator used supported the correct divisors to keep the AGP and PCI speeds in spec @ FSB speeds of 100, 133, 166, and 200mhz. The clock generator chip in question is the ICS 94228. If you check this .pdf file for the 94228 clock gen and look at the table on page #6, it clearly shows the AGP and PCI speeds in spec @ 166mhz FSB and 200mhz FSB. Now, as of yet, these divisors are not supported in the bios as going up to 166mhz FSB, the PCI speed does not fall back down to 33mhz. I was under the impression that if Epox enabled support for this in a future bios, it would be possible to run @ 166mhz and even 200mhz FSB speeds while keeping the AGP and PCI speeds in spec. A recent email reply from a Epox engineer claims that while the clock generator does support the divisors, the KT266A chipset itself does not? Is this true? I thought the chipset was independant of the AGP and PCI divisors, and that this was handled solely by the clock generator and the bios? Could someone explain to me what actually determines the AGP and PCI speeds and if the chipset itself also needs to support the dividers. Thanks in advance...

 

[Mday]

the dividers, or fractional multipliers are part of the core logic chipset's hardware coding. the core logic chipset is the most important part of a computer and handles i/o for the entire system (memory, CPU, etc)... all the bios does is tell you what the numbers can be for you to choose.

the clock generator crystal is only used to determine what a timing the board has. it does nothing else. it's what the motherboard uses to determine what a Hz is, otherwise you get random useless numbers.

just a comment, it's possible to design the motherboard to have the timing of the pci and agp slots independent of the FSB, which is the speed of the i/o between the chipset and the cpu. i don't know about cost considerations since i don't know that much.

so basically: the core logic chipset defines everything. the numbers are derived from the rated speed of the generator chip (which has a crystal in it) to determine actual frequency mathematics.

one could design a board which can use very high frequencies, 500 600 MHz fsb, but you know what, instability. you just can't run the system like that. the noise (emi) and other components not supporting it would cause it to go nutz on you.

 

[Tessel8]

You suggestion of independent clock sources for the FSB and AGP/PCI probably will not work, atleast with current chipsets. Most of the chipsets I have seen expect data busses to be multiples of each other (which your proposal coud still meet) and phase aligned (meaning their clocks arrive at the same time). With 2 independent clock sources, you would have to manually phase align the clock sources and maintain them that way. This can be done, but it isn't easy and may require some pretty expensive components be added to the motherboard.

If the chipsets were designed with asyncronous clock domains on each interfaces, what you are talking about would be alot easier. That may be the wave of the future, but right now I don't know that it is of interest to most.