Question about accumulator based pdm (not really a pwm).

[William Gaatjes]

I am playing with vhdl and created an accumulator based pdm based on an article from the website fpga4fun.
It works great in de simulator, tomorrow i will be testing if it works in real life as well.

Besides that all logic components must be specified to handle high frequencies and that EMC must be taken serious during layout of the coppertraces when designing the pcb, are there more disadvantages ?
I know the pwm frequency also varies depending on the pwm value.
At 8Mhz input clock it seems to vary between 2MHz and 500kHz.
But when just using it to create an analog signal or a dc reference voltage, i do not see a problem.

What are the disadvantages of an accumulator based pwm ?

http://www.fpga4fun.com/PWM_DAC.html

 

[William Gaatjes]

More fun with the fpga :
http://www.bitblit.org/articles/s3more/index.shtml

 

[William Gaatjes]

Turns out this is a delta sigma converter dac.
It is more of a pulse density modulation technique in stead of pulse width modulation technique.
The higher the input value, the more pulses until the output remains high with some fine glitches in between.