quad-pump

[hardwareuser]

How does quad-pumping work in those intel systems? I know that DDR operates on both clock edges, but how do you have 4/clock? Do they just double the clock and work on both edges, or what?

Thanks for any help.

 

[Calin]

Shortly, they send data 4 times per clock cycle. However, if the DDR is working by sending data on both the rising edge and the falling edge of the clock signal, Intel's quad pumped bus uses the clock signal that is sent on 4 lines, every one of those line being time-shifted by a quarter of the cycle time. So, in the end, data is sent at the edge on every one of those time-shifted clock signals.
I am referring to the FSB clock, not the processor one
I read this somewhere, around the introduction of the quad pumped FSB.

 

[BitByBit]

It uses two signals, 90 degrees out of phase with eachother, each of which transmit data on both the rising and falling edges of the clock cycle.

 

[Vee]

Well the FSB is quadpumped, not the memory bus!
The memory bus uses two channels. You do know that the FSB is not the memory bus, I trust?
Otherwise it's roughly as Calin and BitByBit says.
It synchs twice, but sends/reads four times.

 

[hardwareuser]

Thanks for the info!

The FSB is between the CPU and the northbridge, while the memory bus is between the northbridge and the memory, right?

 

[Varun]

Originally posted by: hardwareuser
Thanks for the info!

The FSB is between the CPU and the northbridge, while the memory bus is between the northbridge and the memory, right?

Yup - assuming we are speaking of any x86 other than the A64 which we are in this thread

 

[MetalStorm]

On that note, how does the A64 communicate with memory without a FSB? Is it connected with HT?

 

[Calin]

The so-called FSB is just a high speed high bandwidth connection between two chips. Nothing more, nothing less.
For the Pentium4 and AMD processors up to Athlon64, the FSB is used to communicate between the processor and the chip called northbridge. The northbridge contains the memory controller, integrated video (if any) and so on. The northbridge is also connected to other chips, one of them being called southbridge. The connection is another bus, just that it isn't on the front side.
This second bus can be a low-width high speed bus (like the VIA something), could be integrated into a single chip that is both northbridge and southbridge (like in SIS 735 chipset), or could be a wider lower frequency bus. It could even be PCI bus.
Why the northbridge and southbridge are different? Because one can choose one specific northbridge and one specific southbridge to match its needs. This way, Dell could sell mainboards with one southbridge having 2 IDE 66 channels and 4 USB, 2 IDE 133 channels and 8 USB, or any other combo they seem fit. Works considering most office computers have little needs, so saving one dollar for a lower southbridge would make millions in the grand scheme of things

 

[Calin]

And regarding to the memory and FSB thing, the memory itself has its own bus and protocols, bus and protocols that have absolutely nothing common with the FSB. One could run the memory bus and FSB at different frequencies, one can have (let's just take the general Pentium 4 example) the quad pumped FSB connected thru the northbridge to either single-channel SDRAM, single channel DDRAM, dual channel DDRAM, dual channel RAMBUS or dual channel DDR2.
What the Athlon64 did was move the memory controller from the northbridge on the processor itself

 

[hardwareuser]

MetalStorm, I think the answer to your question is yes.

Thanks for the help, guys.

 

[MetalStorm]

Originally posted by: hardwareuser
MetalStorm, I think the answer to your question is yes.

Thanks for the help, guys.

Ok, but doesn't HT run at 800 or 1000MHz? How come to overclock the memory you have to overclock the HT as well?

 

[BitByBit]

There is no HT link between the processor and memory.
Hypertransport is used to connect the processor to system devices, and to other processors.

Look here.
Notice the memory bus is indeed separate from the HT links.

 

[hardwareuser]

I'm not sure whether it's HT or not. All I can say is that when you set the HTT speed of the motherboard, that's what the RAM is gonna run at (except when you use a memory divider). BUT, the HTT speed alone doesn't go up to 1GHz. It requires a multiplier, which is the LDT. So with a 200MHz HTT, and a multiplier of 5, you get 1000GHz. Since it's full-duplex, it's 2GHz. The end result is that you have the memory running at 200MHz (standard anyway) while the HT runs at 1GHz because of the multiplier.'

Although the diagram suggests a separate bus, there seems to be a suggestion that it is actually the HT.

"HyperTransport technology for high speed I/O communication

- One 16-bit link up to 2000MHz
- Up to 8GB/s HyperTransport I/O bandwidth
- Up to 14.4 GB/s total delivered processor-to-system bandwidth"

http://www.amd.com/us-en/Processors/Pro...ion/0,,30_118_9485_9487%5E9493,00.html

They might've just added the 6.4GB/s bandwidth of the RAM in there to make it look good, or it may really be part of the HT. I have no idea. Someone clue us in?

 

[icarus4586]

The reason that the memory bus frequency is affected by a change in the HTT frequency is the same reason that it would change with FSB freq. In systems with a normal Northbridge, all frequencies (PCI, AGP, memory, even stuff like serial ports) is a multiple of the FSB. In K8 (A64, Opteron, etc.) all that stuff is a multiple of the HTT frequency.

Their quoted 14.4GB/s is a little bit bogus, at least for the desktop Athlon 64. They figure in 2 HTT links, while there really is only one. (HTT theoretical bandwidth: 1000MHz * 2 (full duplex) * 16bits wide / 8 bits per byte = 4000MB/s) (Memory theoretical bandwidth: 200MHz * 2 (DDR) * 2 (dual channel) * 64 bits wide / 8 bits per byte = 6400GB/s)