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Processor Clock Design

C

coolgirl123

Junior Member
Hello friends ( Joined this forum yesterday only )


I am working on project "Pentium processor Clock design "


I have covered almost all parts or aspects of it but there are few
things which are still vague . I would like to discuss them with you


a) Which is the best or latest methodology for minimizing skew of
clock , i found some on Internet but they are old 1 .

b) Well this statement is beyond my reach


" To ensure a 1:1 relationship between the amplitude of the input
jitter and the internal and external clocks , the jitter frequency
spectrum should not have any power spectrum peaking between 500 KHz and
1/3 of the CLK operating frequency "


I worked on the statement but i found my observations contradictory ,
please explain or give me some hints about it


c ) Though there are many PLL Clock drivers but i would like to know
which is best and on the which grounds we rank PLL Clock Drivers


d ) I studied that because of high speed design picture changes but i
want to know what happens to load characteristics . I Couldn't find
any literature regarding it .


Well I would ask more question as soon as i make more progress in my
project


Thanks
 
Originally posted by: blckgrffn
You may want to try the highly technical forum....
Click to expand...

QFT

If I had to guess, I'd say you can minimize skew by making sure that all PCB traces are the same length. Also you can use a TCXO, TCO, or a VCO to keep the clock acurate. As for jitter, you don't want it at a high frequency or else the CPU could see what appears to be an extra clock in the signal. This could effectively double the frequency of the CPU for one clock cycle, which would cause a crash. I think PLLs are rated based on their stability for staying on frequency.
 
" To ensure a 1:1 relationship between the amplitude of the input
jitter and the internal and external clocks , the jitter frequency
spectrum should not have any power spectrum peaking between 500 KHz and
1/3 of the CLK operating frequency "

I am not able to understand this statement
 
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