Problem with some VHDL coding...

[CraKaJaX]

I'm basically done with this project, but it's the first time we are required to input a clock signal. I usually do it in the vector waveform file, but doing it as an input I don't understand how I go about it. I tried putting it in my input signal list as shown:

entity ForBack is
port (
F_B : in std_logic;
Clk : in std_logic;
Q : inout std_logic_vector (2 to 0);
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic
);
end ForBack;

and then I declare it in the port map for one of my D Flip Flops as:

U0: D_flip_flop port map(D=>D(0),Clk=>Clock,Q=>Q(0),Qnot=>QN(0));

And Altera is giving me the error that "Formal "Clk" does not exist."

Can anyone see an obvious mistake here? I tried googling the error, but nothing showed.

Thanks guys.

 

[RESmonkey]

Are you a computer engineer?

 

[CraKaJaX]

Originally posted by: RESmonkey
Are you a computer engineer?

Electrical

 

[RESmonkey]

So that's what I'm going to learn?

 

[Pepsi90919]

Originally posted by: RESmonkey
So that's what I'm going to learn?

you'll dabble in digital systems, it's pretty fun

 

[sciencewhiz]

Shouldn't you reverse clk and clock?

 

[CraKaJaX]

Originally posted by: sciencewhiz
Shouldn't you reverse clk and clock?

As in...

entity ForBack is
port (
F_B : in std_logic;
Clk : in std_logic;
Q : inout std_logic_vector (2 to 0);
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic
);
end ForBack;

U0: D_flip_flop port map(D=>D(0),Clock=>Clk,Q=>Q(0),Qnot=>QN(0));

?

I tried that too. Same error.