Preferred CPU

[jsm]

What CPU do you prefer?

Alpha, HP PA-RISC or Ultra Sparc III? For scalability, I would have to vote for the new rev. of the Compaq Alpha chip. What do you CPU experts think?

 

[Halz]

Sheat man, no responses?

I'll have to cast my vote for the Cyrix III.. its that .15 micron die and throbbing 700MHz of unjustifiable power each person needs!

 

[shiznut123]

ALPHA!!!

 

[jsm]

I didn't figure anyone would respond to this one. With all the bickering between AMD vs. Intel, I didn't think anyone would respond to this. I was hoping that people here didn't only know about x86 CPUs, but I guess I was wrong.

I could have posted this on Ace's Hardware and there would have been a war (with Alpha folks winning of course).

 

[Mustanggt]

ok I will vote for Alpha then LOL.

 

[Halz]

Lemmings.. can you justify your answers? Anyone can spout "Alpha!" and not know what the smeg they are talking about.

 

[gjwild]

Process technology is very important. It is hard to overcome process gap in architecture. To stay in leading position, Alpha should be produced at least at similar or better process than other near future architectures.
Alpha system architecture is also known for good compilers. However, with huge investment in compilers technology induced by IA-64 architecture and overall shift to more sophisticated compiler technology could eliminate any Alpha system architecture advantage.
For unleashing more parallelism, it is needed to reduce length of dependency chains and broke long instruction dependency chains. Immediate operand merging described for x86 architecture is very important. Transforming on-the-fly move conditional based code into predicated could significantly reduce dependency chains. Using stack caching in registers can unleash more parallelism across subprogram call boundaries, by reducing store-load from critical path.
Because instruction set architecture is lacking support for efficient Boolean expression trees high reduction, doing this type of transformation on the fly by hardware will be costly, but more than welcomed.
I think, that even 8-issue architecture implementation will be very complex, but using code-transformation techniques could be extracted reasonable performance gains. Two threads per CPU support could be some insurance for the case, that code transformation techniques, compilers and applications will not live up to expectation for this wide architecture implementation.
From my point of view, it is unlikely, that Alpha architecture should be effectively scaled beyond 8-issue implementations. However, performance of 8-issue implementation could be dramatically boosted by instruction set extensions, rather that going for wider implementation.
Another very interesting approach could be chosen in combination with multi-threading - creating ultra pipelined high-frequency implementation. While single-thread performance will be not dramatically penalized, throughput could be increased dramatically. However, logic, circuit design, layout and other engineering factor makes this task extremely uneasy.