- Oct 9, 1999
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Power specs for 1.2 to 1.5 GHz Athlons:
- Thread starter NFS4
- Start date
Wow. 46 A @ 1.75 V? for a 1.5 GHz athlon.
That works out at 80 W :Q - they badly need a die shrink.
That works out at 80 W :Q - they badly need a die shrink.
they are gonna rework the core with more pipeline stages. the mustang core is supposed to add 2 stages for higher clock speeds.
One of these days they are going to make a reversible power supply for the Athlon so in winter it can blow the hot air over you. Maybe it can recharge my hot water bottle or something.
Ridiculous. AMD must release Mustang core with Athlons approaching frequencies of 1.5GHz. Personally I wouldn't buy a CPU which dissipates more than 50-60W. But I'm afraid that with higher-speed Thunderbirds and especially Intel's P7 core, we're entering to times of really, really hot CPUs and more exotic cooling solutions.
And Mustang must not dissipate even close as much as Tbird if AMD ever wants to introduce a mobile Athlon chip.
And Mustang must not dissipate even close as much as Tbird if AMD ever wants to introduce a mobile Athlon chip.
Heck, with the CPU going full bore (overclocked), and the video card cranking out heat as well, I just turn the heat off in the winter when I'm playing 3D games. 
Actually, I usually end up opening the window when the temperature is below 50 since two computers in that little room heat it up pretty well!
Actually, I usually end up opening the window when the temperature is below 50 since two computers in that little room heat it up pretty well! 
?? they have stepping T-Birds running at 1.5 ghz? or are those derived from mathematical formulas..
if they can get CURRENT stepping processors up to 1.5ghz, WHY the hell are they adding 2 stages to the pipeline in the mustang line of processors?? all those little tweaks alone will be able to improve the speed somewhat.. not to mention lower the power draw.
if they can get CURRENT stepping processors up to 1.5ghz, WHY the hell are they adding 2 stages to the pipeline in the mustang line of processors?? all those little tweaks alone will be able to improve the speed somewhat.. not to mention lower the power draw.
AMD has had 1.5GHz engineering samples in the lab for around 8 months now, but those are mostly kyrotech cooled. Their adding 2 stages to the pipeline purly to allow higher mhz scaling. Think about it, some computer illerate joe-bo goes into the computer store, sees a 1.7GHz Intel P4 and a 1.4GHz T-bird. Even though the t-bird is much faster in real world use, he sees 1.7GHz and buys that one.
"AMD has had 1.5GHz engineering samples in the lab for around 8 months now, but those are mostly kyrotech cooled."
first off, how do you know this?
second, yeah that makes sense. I never expected the non-tweaked t-bird/duron core to hit 1.5ghz air cooled.
"Their adding 2 stages to the pipeline purly to allow higher mhz scaling."
yeah I know this.. I was hoping that they wouldn't need it to get to 1.5ghz though. it would have said something good about their team of engineers over there..
first off, how do you know this?
second, yeah that makes sense. I never expected the non-tweaked t-bird/duron core to hit 1.5ghz air cooled.
"Their adding 2 stages to the pipeline purly to allow higher mhz scaling."
yeah I know this.. I was hoping that they wouldn't need it to get to 1.5ghz though. it would have said something good about their team of engineers over there..
they did a great job though, the p4 is a 20 stage pipeline and on a .18 micron process can do only 1.5 ghz. The mustang will go higher with only a 12 stager
"they did a great job though, the p4 is a 20 stage pipeline and on a .18 micron process can do only 1.5 ghz."
again, where did you come up with that info?
and also, according to Fandu, the chips that hit ~1.5ghz were running with the Kyrotech cooler. does this mean that the Kyrotech cooler was needed to take all that heat from the insane power consumption, or just for the core to clock that high (ie an overclock).
again, where did you come up with that info?
and also, according to Fandu, the chips that hit ~1.5ghz were running with the Kyrotech cooler. does this mean that the Kyrotech cooler was needed to take all that heat from the insane power consumption, or just for the core to clock that high (ie an overclock).
Soccer-
Can't say for sure, but I believe the info on the 1.5 Athlon came from Kryotechs announcemnet
Can't say for sure, but I believe the info on the 1.5 Athlon came from Kryotechs announcemnet
Do any of you know what purpose a pipeline fulfills?
You could make an Athlon with a 5-stage pipeline and clock it up to 5 GHz. I wouldn't matter.
They don't need to add 2 stages to make the Athlon go to 1.5
The reason why the P7 core will run at 1.5 GHz has nothing to do with its 20-stage pipeline. On the contrary, the P7 will ramp near the 10 GHz area. By then AMD will be releasing a new core to succeed to Athlon.
isnt it the more pipeline stages the less work is done per cycle, so the CPU has to do more cycles so the mhz is higher.
"so the CPU has to do more cycles so the mhz is higher."
that part of your sentance is incorrect. the CPU CAN do more mhz, becuase it does LESS per clock cycle.
however the P3 manages to compete very well with the Athlon with a 12 stage pipe, (perhaps that's one reason why AMD chose 12 for this core? to help get more optimization out of programs that are written for 12?).
that part of your sentance is incorrect. the CPU CAN do more mhz, becuase it does LESS per clock cycle.
however the P3 manages to compete very well with the Athlon with a 12 stage pipe, (perhaps that's one reason why AMD chose 12 for this core? to help get more optimization out of programs that are written for 12?).
Maybe one of you smart guys can tell me what the hell is stepping (like CB0) and how the hell is it related to clock speed or how the hell pipeline length is related to clock speed?
I may be stupid, but I wasn't born that way
What kind of Power Supply would you need for one of those puppies? would a current Socket A mobo work?
digitalalgorithm- What the HELL are you talking about? Please, put the pipe down.. Slowly, as to not hurt yourself..
I've also heard AMD has 1.5GHz samples in the lab, long ago.. I do not doubt it one bit..
What officeboy said. They tweak the core, move things around(slightly), etc. in order to be able to allow better efficency.. If you take a look at the P3 stepping revisions, you'll notice that the die shrunk slightly on a few of them ..
I don't think AMD will be releasing a 1.5GHz Thunderbird.. Although it would be totally possible.. I think the reasonable limit of the Thunderbird core is 1.4GHz.
The P4 at 1.5GHz dissipates like 55W.
someone come in here and set digitalidiot straight, and explain to DeaththroweR
I've also heard AMD has 1.5GHz samples in the lab, long ago.. I do not doubt it one bit..
What officeboy said. They tweak the core, move things around(slightly), etc. in order to be able to allow better efficency.. If you take a look at the P3 stepping revisions, you'll notice that the die shrunk slightly on a few of them ..
I don't think AMD will be releasing a 1.5GHz Thunderbird.. Although it would be totally possible.. I think the reasonable limit of the Thunderbird core is 1.4GHz.
The P4 at 1.5GHz dissipates like 55W.
someone come in here and set digitalidiot straight, and explain to DeaththroweR
"I don't think AMD will be releasing a 1.5GHz Thunderbird.."
well it's for sure we won't with this current core revision/stepping and cooling, however Kyrotech could easily release a 1.5g!
with the next stepping (mustang, palomino, and whatever the new Duron is called) it probably will.
well it's for sure we won't with this current core revision/stepping and cooling, however Kyrotech could easily release a 1.5g!
with the next stepping (mustang, palomino, and whatever the new Duron is called) it probably will.
digitalalgorithm, soccerman, hans007
You all seem to not fully understand what pipelining does.
In any logic circuit (MPU's included) the number of logic gates in series determines the frequency the circuit can operate (along with the frequency the gates themselves can operate at.)
When you pipeline 2 things happen. First you break up a long string of logic gates into much shorter strings called stages. This allows you to clock the circuit at higher frequencies (as fast as the longest or "critical" stage can operate.)
This by itself accomplishes nothing since instead of performing 1 operation in 1 clock you are performing that same operation in several clocks. The absolute time it takes to perform the operation remains unchanged.
This is where the second part of pipelining comes in. Let's say you have a 4-stage pipeline. You do not have to wait until an instruction makes its way through the whole pipeline before starting a second instruction. As soon as the first instruction has passed through the first stage in the pipeline a second can enter. So after 4 clock cycles you have the following instruction 1 (I1) is complete I2 has completed up to stage 3 (S3), I3 has completed S2, I4 has completed S1.
So you should now be able to complete 4 times as many instructions as the original 1 stage circuit. You are not doing less work per clock in a longer pipeline just less work per stage in each clock. Because you have more stages you may in fact be doing more each clock.
There is an excellent thread at ars discussing this. (It starts of talking about the G4 processor but turns into a discussion about pipelines with a number of excellent posts.)
http://arstechnica.infopop.net/Open...amp;s=50009562&f=77909774&m=224092771
(the above is all 1 link)
You all seem to not fully understand what pipelining does.
In any logic circuit (MPU's included) the number of logic gates in series determines the frequency the circuit can operate (along with the frequency the gates themselves can operate at.)
When you pipeline 2 things happen. First you break up a long string of logic gates into much shorter strings called stages. This allows you to clock the circuit at higher frequencies (as fast as the longest or "critical" stage can operate.)
This by itself accomplishes nothing since instead of performing 1 operation in 1 clock you are performing that same operation in several clocks. The absolute time it takes to perform the operation remains unchanged.
This is where the second part of pipelining comes in. Let's say you have a 4-stage pipeline. You do not have to wait until an instruction makes its way through the whole pipeline before starting a second instruction. As soon as the first instruction has passed through the first stage in the pipeline a second can enter. So after 4 clock cycles you have the following instruction 1 (I1) is complete I2 has completed up to stage 3 (S3), I3 has completed S2, I4 has completed S1.
So you should now be able to complete 4 times as many instructions as the original 1 stage circuit. You are not doing less work per clock in a longer pipeline just less work per stage in each clock. Because you have more stages you may in fact be doing more each clock.
There is an excellent thread at ars discussing this. (It starts of talking about the G4 processor but turns into a discussion about pipelines with a number of excellent posts.)
http://arstechnica.infopop.net/Open...amp;s=50009562&f=77909774&m=224092771
(the above is all 1 link)
hans007 - WTF? If you can please give me a link telling how they would add two stages to the core, please tell me, because other than rumours, this is news to me. I kinda doubt it. If it were as easy as you say, why didn't intel do it to the P6 core? Hymmmmm?
And, the great post at arstechnica linkified.
For those of you who can afford it, pick up a copy of "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson. I picked mine up just recently. If you want to know what you are talking about, DO RESEARCH. Read books. Read GOOD articles about computer architecture (anands is a great site, I love it to death, but its not a computer architecture resource of the same caliber as others), not little pansy ones. aceshardware has great ones. So does arstechnica. Both sites GIVE THEIR SOURCES (aka, a bibliography). Always a good thing. Another one I read whenever there is an update is realworldtech, most notably, the articles by Paul DeMone.
digitalalgorithm - stop neffing.
And, the great post at arstechnica linkified.
For those of you who can afford it, pick up a copy of "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson. I picked mine up just recently. If you want to know what you are talking about, DO RESEARCH. Read books. Read GOOD articles about computer architecture (anands is a great site, I love it to death, but its not a computer architecture resource of the same caliber as others), not little pansy ones. aceshardware has great ones. So does arstechnica. Both sites GIVE THEIR SOURCES (aka, a bibliography). Always a good thing. Another one I read whenever there is an update is realworldtech, most notably, the articles by Paul DeMone.
digitalalgorithm - stop neffing.
Thanks for putting that in a link for me.
I have also heard rumors of additional stages in the Mustang.
Adding a stage should not be that hard. In theory it is as simple as putting in a latch. In practice you have to find a place that a latch could actually go. I think Intel added stages to the P5 and Motorola is adding stages to the G4.
The problem with adding stages is that it probably will not help if the pipeline was well designed to begin with. Since your processor can only run as fast as the longest stage allows, breaking up a stage other then the longest doesn't allow you to increase the clock speed at all.
It could well be that all the stages in the P6 are so close to the same length that breaking them up would do no good.
I think AMD may be doing something like reorganizing the pipeline so that 2 long stages become 3 shorter ones. If you just break up a stage then another stage will become the bottleneck and there is no guarantee that that stage isn't almost as long as the one you just broke up.
I have also heard rumors of additional stages in the Mustang.
Adding a stage should not be that hard. In theory it is as simple as putting in a latch. In practice you have to find a place that a latch could actually go. I think Intel added stages to the P5 and Motorola is adding stages to the G4.
The problem with adding stages is that it probably will not help if the pipeline was well designed to begin with. Since your processor can only run as fast as the longest stage allows, breaking up a stage other then the longest doesn't allow you to increase the clock speed at all.
It could well be that all the stages in the P6 are so close to the same length that breaking them up would do no good.
I think AMD may be doing something like reorganizing the pipeline so that 2 long stages become 3 shorter ones. If you just break up a stage then another stage will become the bottleneck and there is no guarantee that that stage isn't almost as long as the one you just broke up.
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