Post-silicon: III-V and Ge may not be used at foundries' 7nm node

[witeken]

I compiled some recent and less recent information about companies' 10 to 5nm nodes.

Next Channel Materials? -- What will replace silicon and when will it happen? There are no simple answers, but something has to be done.

So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm and 7nm, but that by itself may not provide enough of a performance boost. So to help enable faster chips, the industry must address one critical piece of the overall finFET puzzle—the channel materials.

In fact, chipmakers are currently revising their channel-materials efforts amid a multitude of challenges in the arena. For some time, the industry has been searching for an alternative material to replace silicon in the channel. In the channel alone, silicon could run out of steam at 7nm.

Originally, chipmakers were looking at two material types, germanium (Ge) and III-V, for the channel at 7nm. Ge and III-V could provide a mobility boost, which refers to how fast the electrons can move in the channel. But Ge and III-V are more complex than previously thought and may not be ready for 7nm.

Instead, the industry is leaning toward a more evolutionary approach, with silicon-germanium (SiGe) for PFET and tensile silicon for NFET. Ge and III-V are still in the running, if the industry can make a breakthrough in this area.

Ge and III-V are fast but difficult to implement. “Growing InGaAs on silicon is challenging. The lattice mismatch is the biggest hurdle with III-V materials,” Banna said. “You can do germanium, but it’s too radical of a step. The challenge is to have a good oxide on germanium.”

From another Semiconductor Engineering article, this is what Bohr said about the issue:

Bohr: Germanium is clearly the leading candidate for the p channel in the device. N channel is a tougher problem. You might have to look at more exotic III-V materials. But changing the channel materials is a big increase in the complexity, not only because it will likely have to be different between p and n, but you may have to change the material in the silicon substrate. Then, you have to worry about how you get this new material on silicon. And you have to worry about making transistors for a very wide span of applications, from high performance to very low leakage. So III-V channels must not only provide high performance capabilities but also very low leakage. At very low leakage, you are limited by band-to-band tunneling. Sub-threshold leakage may be more of a problem with some III-V materials. So developing a universal, or widely useful, transistor from high performance to very low leakage is quite a challenging task.

SE: Some say the III-V materials have been pushed out or delayed. Any thoughts on that?

Bohr: Other companies may choose to push out the adoption of III-V, because all of the problems have not been solved for the 10nm generation. Tool readiness doesn’t seem to be the issue. It’s mostly device physics.

To me it seems clear that Intel will introduce Ge and III-V at the 10nm node. Intel has been R&Ding post-silicon transistors for many years, and also according to Bohr at IEDM, 10nm doesn't have yield issues. It now seems that companies like Global Foundries and maybe TSMC may not have those technologies ready for their 7nm node, and even Intel could have decided to shy away from using it a few years ago.

SemiEngineering has conducted an interview with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at research center Imec, about 7nm and 5nm nodes.

One-On-One: Aaron Thean -- Imec’s process technology and logic devices guru talks about 7nm and 5nm parasitics, new materials and transistors, and where are the biggest unknowns.http://semiengineering.com/one-on-one-aaron-thean/

SE: Some say the finFET could run out of gas when the fin width goes below 5nm. Is that the case and what’s next?

Thean: Today, the fin thickness for finFETs is around 7nm to 8nm. You can maybe go to 5nm at the next node. At 5nm and beyond, we will need to look at more exotic channel materials.

SE: What are the challenges to bring III-V materials into the channels?

Thean: The challenges are still the materials and the gate stack. III-V doesn’t enjoy the same benefits as silicon in terms of the amount of time that people have been working on it. So it suffers from a lack of maturity. III-V does bring some performance benefits, however. The key question is bandgap. It is a very narrow bandgap material. So if you want to actually run it at the operating voltages that we have today, you might get a fair amount of band-to-band tunneling. So that gives you an increase in leakage. So that’s something we need to understand. Second, the gate-stack reliability is a little bit more challenging than silicon. That needs a little bit more work. The third thing is scalability. When you squeeze a III-V channel down, you do see a quantization effect. There is a penalty to pay there. So those three things mean that a III-V device may have to be in a unique architecture.

SE: When will III-V channel materials appear in IC designs?

Thean: We are still working on it. But we are working on it from a 5nm standpoint rather than 7nm. As I mentioned before, the time is getting close for 7nm. The research for 7nm must be done by the 2016 time frame.

SE: The industry is talking about germanium and/or silicon germanium in the channels at 10nm/7nm. What are the challenges?

Thean: Germanium and III-V are both being worked on. Germanium, being a group IV material, is conducive to co-integration with silicon. Silicon germanium could come in earlier. Silicon germanium is a little easier to handle than germanium. But if you want to get a boost in silicon germanium, you would have to bump up the germanium content and then you start to approach pure germanium. Germanium also has a very narrow bandgap. It also suffers from the same problem in terms of band-to-band leakage. That means it has to be co-integrated with something else.

Definitely worth a read, I'm not going to copy and paste the whole article, obviously...

One thing to note is that Imec already showed a III-V FinFET transistor at the end of 2013: Imec Demonstrates World’s First III-V FinFET Devices Monolithically Integrated on 300mm Silicon Wafers

The "world's first" part can be debated since companies like Intel are very quiet about their R&D, of course. For example, we know that as of mid-'11, Intel has grown III-V on bulk silicon, with high-k integration done and 3D partially done (N and P on same wafer was not yet done).


Intel's 10nm node will introduce a new transistor innovation and is as far publicly known still scheduled for volume production early 2016, or maybe a bit earlier. TSMC has stated it will start HVM of its 1st FinFET node in Q3'15, and volume production of its 2nd FinFET node, called 10nm, in 2017 (so their 7nm node, possibly wihout Ge and III-V, will ship to customers early next decade or so).

Another part of the node equation, the cost per transistor, is still to be determined. Early reports from companies like Nvidia and ARM noted a stagnation, but TSMC may have potentially improved that metric, but in any case the cost per transistor seems to be too bad for GPUs: According to Fudzilla, this is because:

From what we know AMD and Nvidia won’t be releasing 20nm GPUs ever, as the yields are so bad that it would not make any sense to manufacture them. It is not economically viable to replace 28nm production with 20nm.

This means the real next big thing technology will be coming with 16nm / 14nm FinFET from TSMC and GlobalFoundries / Samsung respectively, but we know that AMD is working on Caribbean Islands and Fiji as well, while Nvidia has been working on its new chip too.

The quite massive delay of FinFET for TSMC due to yield problems means that 16nm may also face a low adaption for GPUs. 28nm is here to stay for a very long time. So with that in mind, it remains to be seen how EUV will improve the economics of the currently rapidly increasing cost per wafer and thus $/transistor. At least for Intel, that won't be an issue, even at 7nm without EUV.

 

[III-V]

To me it seems clear that Intel will introduce Ge and III-V at the 10nm node.

You mean "will not," right?

Another part of the node equation, the cost per transistor, is still to be determined. Early reports from companies like Nvidia and ARM noted a stagnation, but TSMC may have potentially improved that metric, but in any case the cost per transistor seems to be too bad for GPUs: According to Fudzilla, this is because:

The quite massive delay of FinFET for TSMC due to yield problems means that 16nm may also face a low adaption for GPUs. 28nm is here to stay for a very long time. So with that in mind, it remains to be seen how EUV will improve the economics of the currently rapidly increasing cost per wafer and thus $/transistor. At least for Intel, that won't be an issue, even at 7nm without EUV.

Cost/transistor has come down on 20nm. Earlier projections were based on the process having a looser minimum metal pitch, but they ended up tightening that up.

As far as 20nm goes, it just wasn't offered as a flavor usable by high performance GPUs.

 

[Arachnotronic]

The quite massive delay of FinFET for TSMC due to yield problems means that 16nm may also face a low adaption for GPUs. 28nm is here to stay for a very long time. So with that in mind, it remains to be seen how EUV will improve the economics of the currently rapidly increasing cost per wafer and thus $/transistor. At least for Intel, that won't be an issue, even at 7nm without EUV.

I would think that dGPUs would be one of the first applications to move to 16FF+.

 

[III-V]

I would think that dGPUs would be one of the first applications to move to 16FF+.

After Apple has its turn, of course.

 

[witeken]

You mean "will not," right?

No.

“That still is 3 and a half years that we have built and experience and also shipping. I'm not going to tell you what the next innovations are, but our roadmap is full, because to continue to improve transistors, you have to make substantial improvements. And we plan to do that, while other people are working on perfecting their FinFET devices, and we're gonna be moving on to looking at what comes next.” --William Holt, Intel, IM’14

Intel has had the highest performing transistor and transistor technology (both at iso node, iso feature sizes and iso time) for the past decade, and I don't think that Intel will go with anything less than the best. It's like with FinFET vs UTB/FD-SOI. Of course Intel went with FinFET, but there was talk that other companies would go with the other option. Now there's similar discussion. That's how I see it, at least. Intel's transistor research should not be underestimated.

I would think that dGPUs would be one of the first applications to move to 16FF+.

I guess my editing made it ambiguous, because I wanted to include that prospect about 28nm from this article (http://semiengineering.com/manufacturing-and-packaging-changes-for-2015/). 28nm will be a very popular node for the time to come, but the leading edge will of course move on.

 

[III-V]

No.

I'm not seeing how you reached that conclusion. He worded things such that there are no indications of what Intel is doing. Honestly, given that he admitted the issues haven't been solved, and the interview was rather recent, past the point where it could be chosen for use at 10 nm anyway, I'm interpreting that as Intel not using it at 10 nm.

 

[ShintaiDK]

After Apple has its turn, of course.

And Qualcomm.

 

[witeken]

I'm not seeing how you reached that conclusion. He worded things such that there are no indications of what Intel is doing. Honestly, given that he admitted the issues haven't been solved, and the interview was rather recent, past the point where it could be chosen for use at 10 nm anyway, I'm interpreting that as Intel not using it at 10 nm.

I don't interpret is like you do. But as you can read, I'm not ignoring the idea that they shied away from Ge and III-V, but you can clearly see that that isn't their goal:

http://download.intel.com/newsroom/...esearch_Enabling_Breakthroughs_Technology.pdf

Page 8, 10, 11vs12. Si(Ge) isn't even mentioned.

Totally unrelated, but while doing some digging I stumbled across this comment from Mark Bohr:

During the press briefing this morning you were asked about the name change of what used to be the 16nm node, and that you are now referring to as 14nm node. Your answer to that was you managed to increase density. Could you elaborate a little bit more on that ?

MB : Only if you promise not to tell our competition ! But the name change is not just semantics. We took a close look at what our original density goals were for that generation, identified ways to do even better than normal in terms of scaling, and thus renamed it from 16 to 14.

http://www.behardware.com/articles/877-1/idf-interview-with-intel-s-mark-bohr.html
Also from that interview:

In 2005, Intel's research group published a paper regarding the usage of III-V materials [materials from columns III and V of the periodic table of elements], at that time Indium and Antimony in order to build compound semiconductors [using two materials instead of one, silicon]. Can you talk a bit about further research on that topic?

MB : Yes ! Our research group has published a series of papers over the past four or five years on even better III-V channel transistors using I think Indium-Gallium-Arsenide [InGaAs] and Indium-Phosphide [InP], so, we're making steady progress on that front as a way to provide higher mobility transistors, and higher mobility can be translated to lower operating voltage, which means lower power. So that's one of several interesting transistor directions that our research group is exploring. Other transistors options include, instead of a finfet, a nanowire type structure for example that you can do with silicon or germanium.

And for the sake of completeness:

Any comment on which one you see having the most short term potential? It would seem nanowire structures are a bit farther off than using III-V materials?

MB : I'm not going to comment on which is more or less likely. We're exploring a range of transistor options and exactly which one ends up being selected and best meets our needs is something we'll disclose later. But our research group, their job is to cast a wide net, explore many options and yeah, maybe some of them just don't work out, but a few of them do.