Possible solution to DDR2 high latencies?

[lexxmac]

Not long ago I posted a thread about using SRAM for the row cache on DRAM (originally found on LostCircuits), and specifically I was thinking DDR(1). Well, the latency on DDR is not all that bad, and doesn't need much improving for mainstream frequencies. Well, along comes the first bits of information about DDR2 and what do we have? Latencies out the rear. DDR2 includes some great advances like on-die termination, a quad-pumped speeds, and the rise of BGA packaging. Why not throw in SRAM row caches? Considering that doing so would not alter the compatibility of the product and that the increase in die size is very negligible, why not? Wouldn't that solve the DDR2 latency problems? Have I missed something here?

 

[Falloutboy]

it might help a bit but from what I know of SRAM it take 8 times as much die space as SDRAM, this is why caches take up so much die space. so lets you throw 256k of SRAM on each ram chip I bet you increase the size of the chip by atleast 25%. which means about a 25% hike in price not including the R&D that would have to be payed for so your looking at a 40-50% jump in prices.

 

[lexxmac]

Well, the article I am refering to on lost circuits might be a point of reference. The added die space was about 2%, and there is essentially no need to reinvent the wheel in R and D, as the implementation is simple. As much of a question my original post was, I really think the points you mention are either wrong or not an issue. If 8 times is correct, then it would take the same die space for 8MB as 512 KByte which is a rather large chip, and RAM prices would go through the roof, but that's not the case. SRAM is larger, and uses 5 or 6 transistors per bit, and DRAM uses one transistor and one capacitor, but you have to understand that different densities are possible.

 

[Sahakiel]

I seem to remember a similar topic some time ago in reference to DDR2 latencies. If I remember correctly, DDR-II has the exact same latencies as DDR.

 

[lexxmac]

Well, I don't know where you heard that, but to remove an doubts I'd point you to an article right here on anandtech:

http://www.anandtech.com/memory/showdoc.html?i=1977

4-4-4 timings @ PC4300 (DDR2 of course) doesn't sound all that great to me...

 

[Mark R]

4-4-4 timings @ PC4300 (DDR2 of course) doesn't sound all that great to me...

Which is equivalent to 3-3-3 timings at PC3200. This is exactly the same as most DDR memory. The numbers are higher because the clock speed is higher, not because the latency is higher.

There are small volumes of 'niche' memory which offers more aggressive timings. This is not a significant product line for most manufacturers, and in a lot of cases uses chips specially selected by the module OEM - such products should not really be compared to the first release of a new technology. Don't fret, in due course specialised variants will appear.

 

[lexxmac]

Well, DDR2 is quad pumped and so the internal banks are running at 133MHz for PC4300 DDR2 (533 effective), the same internal clock as PC133 SDRAM and DDR1-266 modules which both have had 2-2-2 timings for a long time. DDR is just like striping two drives in a RAID array, and DDR2 is just 4 "drives" where the drives are really just banks of memory. All I'm saying is for the low cost of adding SRAM row caches, it sounds like a great idea to try out.

 

[Sahakiel]

I do believe DDR-II runs the logic at 2x the clock. If that's the case, 4-4-4 timings really isn't all that bad.

 

[Odeen]

Originally posted by: Sahakiel
I do believe DDR-II runs the logic at 2x the clock. If that's the case, 4-4-4 timings really isn't all that bad.

It's rather RAMBUS-ey. Wide pipe, but a very long one - i.e. lots of bandwidth but high latency.

 

[lexxmac]

Wouldn't SRAM row caches be a good solution to speed up latencies?

 

[Mark R]

They're not a bad idea at all. Similar techniques have been used in the past with VC-SDRAM and ESDRAM both of which used a cache type system - though there were some differences.

I think part of the problem is that RAM is a bulk commodity with very little profitability (if any) for the manufacturers. They can't afford to tool up a production line for what would essentially be a niche market, given that the JEDEC specifcations are now relatively firm. Another point is that SRAM is a very different design to DRAM - I don't think the 2 are easy to manufacture together on the same die.