Polysilicon gates?
- Thread starter CTho9305
- Start date
. Most fabs at the moment use poly silicon. Intel WANT to change to metal to reduce the leakage current.
DrPizza
Administrator Elite Member Goat Whisperer
Why wouldn't they discuss what the material was? Maybe I'm naive, but with x-ray spectroscopy and a dozen other methods, it wouldn't be difficult at all to determine the exact composition of the material. While I probably won't get to know, any company with the money to invest in research should be able to determine fairly rapidly what they're using, once they get a chip to check.
DrPizza
Administrator Elite Member Goat Whisperer
Duh, I just answered my own question. If they don't tell until the chips are released, other company's R&D will lag behind further.
Not quite polysilicon. In the polymer chemistry world, the longest silicon polymer chain ([SiR2]n R= alkyl,phenyl) has been about 12-15 repeat silicons in a row. Beyond that silicon tries to rearrange itself to smaller cyclic rings. As the crystal (for fabs), silicon is not considered a polymer.
The article preludes to the end of the Si-O insulator for the transitor on the chip fab, which leads to the a new metal (mystery) fab. I think that it could be a component of ITO (indium-tin-oxide). These compounds have been around for quite a while in the research/academia realm. I guess that they finally found a magic mix to use.
The article preludes to the end of the Si-O insulator for the transitor on the chip fab, which leads to the a new metal (mystery) fab. I think that it could be a component of ITO (indium-tin-oxide). These compounds have been around for quite a while in the research/academia realm. I guess that they finally found a magic mix to use.
Polysilicon ha nothing to do with polymers. "Poly" is short for polycrystalline. Basically it is "bad" sillicon deposited under conditions where it does not grow epitaxially (i.e. it is granular and not a single crystal).
It's not exactly a secret what Intel uses, there's a paper on the process pretty much every year in Dec. at the IEDM Symposium. It's currently a cobalt salicide - which is a form of polysilicon.
I was thinking in the chemist's viewpoint of the term "poly," organic types of repeating units, not the huge inorganic matrix.
Interesting...Instead of oxidizing the surface of the silicon to create the gate, they use another metal atom, such as cobalt, titanium, or possibly nickel and palladium.
check out this webite
CoSi2
Interesting...Instead of oxidizing the surface of the silicon to create the gate, they use another metal atom, such as cobalt, titanium, or possibly nickel and palladium.
check out this webite
CoSi2
Cobalt salicide isn't the gate material they are talking about. Currently, the gate is made up of silicon and silicon oxide. Silicon for the actual gate and SIO2 for the insulator. They are talking about a change of both the gate material and the insulator. I sure hope it works out, but then, if I'm not biased, then I must be insane...
Alright alright, much confusion in this thread it seems to me. I?ll attempt to summarize what's really going on since I actually work in the process area that forms this structure. I will only speak of a generic process since obviously the details are different and protected for each individual company.
Today's gate stack is formed by LPCVD deposition of polysilicon over a thermally grown Si02 gate oxide which lies directly on the channel region of the silicon substrate. Pressure and temperature play key roles in determining the grain size of the polysilicon during deposition. Grain size can effect the conduction ability of the gate as well as it's ability to hold and activate dopant within the gate and not allowing it to segregate and pile up at or in the oxide.
After formation of the gates stack photoresist is spun on (likely with an anti-reflective component at some point)and patterned. The alignment and control of critical dimensions at gate poly is one of the most critical photo steps of the entire process, for CMOS logic at least. Alignment control on the order of less than 3nm of overlay tolerance is not unheard of. After litho the gate stack is etched using reactive ion etching to achieve very anisotropic profiles. At this point in modern self aligned CMOS the source/drain extension regions will be formed by ion implantation. Since PMOS and NMOS transistors obviously require different species to be implanted an additional 1 or 2 lithography steps will mask off either the NMOS or PMOS while the other is implanted at a fairly light dose. The gate stack itself serves to provide a mask over the channel region preventing the implanted dopants from reaching it. Thus the reason the process is called self aligned, rather than relying on an aligned layer of resist we can use the gate itself.
Following formation of the SDE (also called LDD, although that moniker is not correct considering the level of dopant we are putting in today?s devices) LPCVD silicon nitride is deposited conformaly. This nitride is etched in an extremely anisotropic dry etch which only attacks horizontal surfaces resulting in the rectangular gate having sidewalls consisting of nitride. This step is usually referred to as spacer etch and is very critical as it will define the actual physical dimensions of the source drain extensions. Again the wafer is ion implanted and again the PMOS devices are separated from the NMOS through lithography patterning. This time the dose implanted is extremely heavy, the heaviest throughout the entire fabrication process. Having heavily doped silicon for your source/drain is important as the resistivity of silicon is reduced as dopant levels increase. You don't want your transistor switching speed limited by the R inherent in your source/drain. At the same time as the dopants are forming the source/drain they are being stopped from going into the channel by the gate again. This step is very critical though as we want those dopants to also dope our gate very heavily to result in a fairly good conductor. The exact dose delivered also has to provide a profile which will tailor the fermi potential of the gate to lead to optimal balance in the operation between the nmos and pmos devices (i.e. pmos Vt = -1v, nmos Vt = 1v). The only way to achieve this without degrading your channel mobility with excessive Vt adjust implants is to dope the PMOS gates with a p-type dopant (B) and the NMOS gates with a n-type dopant (As, P).
After implantation a blanket layer of cobalt is deposited onto the wafer. When heated through rapid thermal anneal (basically flash lamps) the cobalt will react to form CoSi and CoSi2. Remember that we still have our nitride spacers in place and Co will not react with the nitride. This prevents the gate silicide from shorting to the source/drain silicide. We call this process material salicide which stands for self-aligned silicide. As other posters mentioned the salicide serves to greatly reduce the contact resistance of the source/drain as eventually we will have to land metal contacts onto these to form electrical connections. The salicide also has a much lower sheet resistance than the poly gates important since some poly lines serve as the gates for multiple transistors and must make relatively long runs, R is a function of length (R=rho*length/area).
So now that we understand how a gate is formed today, let's talk about what we will be doing tomorrow. First the silicon dioxide layer that serves as the insulation between the gate and the channel of the silicon substrate. As you reduce the size of your transistors you end up requiring a strong vertical electric field to adequately control the channel. If you don't have sufficient control you will end up with problems such as not being able to ever shut off your NMOS transistors. To increase this control there are several factors which process designers can play with, but the one with the most direct impact is to reduce the thickness of the gate oxide. Control of an electric field is really nothing more than the formation of a capacitor with the two conductors being the gate itself and the silicon substrate and the insulator being the oxide. Remembering back to basic electronic theory capacitance is inversely proportional to the thickness of the dielectric between your conductive plates. So we reduce the oxide thickness, and we have done so since the beginning of MOSFET processing. Today however we are down to thicknesses less than 20 angstroms, which represent only about 4-5 atomic layers of SiO2. At this thickness there are quantum effects which cause electrons to be able to transverse the physical barrier of the oxide and travel without much hindrance from the channel to gate. If this happens we have high gate leakage and have lost the ability to shut off our transistors. We've tried to make our oxides better quality to prevent this through the reduction of contaminants and some additional tricks like nitridizing the oxide. However silicon dioxide simply will no longer serve its purpose in the future as we continue to shrink. So we need to replace SiO2 with a material that has a higher dielectric constant. If it has a higher constant that means we can use greater thickness of the material and still have the same electrical properties as a thin layer of oxide. Oxide was nice since we could just heat the wafers in an oxygen ambient environment to form it. These new 'high-k dielectrics' will have to be deposited. Likely by atomic layer deposition, ALD. The leading candidate in terms of compatibility with silicon and processing ease is hafnium dioxide. It?s still unclear whether we will put down a thin SiO2 layer between the substrate and the hafnium.
Next there is the gate material itself. With each generation it is necessary to implant a greater and greater concentration of dopant into the gate in order to reduce it?s resistivity and optimize it?s electrical characteristics. Since we are using a silicide to basically turn the polysilicon into a sort of metal itself we think to ourselves, why not just use some form of metal in the first place. It?s easy finding a metal with good conductivity. The hard part goes back to what I said about having to match Fermi work functions to match both the NMOS and PMOS transistors. A material which could serve as a gate material for both is known as a mid-band gate material. The only mid-band materials that have been found aren?t very easy to integrate into our processes. And since from the small portion of the process I outlined above you can see our process is complicated enough as it is we would like to find something simple. So it?s looking more and more likely that we will have to use 2 separate metals, one for the PMOS gates and one for the NMOS gates. Intel?s press releases simply states that they feel they have found compatible materials which they feel they can integrate into their process to serve these roles at the 45nm node.
Sorry for the length of the post, I just thought it might help some people who don?t really have a strong process background to understand what is going on and how it relates to the issues being discussed here.
-Not speaking for any company
Today's gate stack is formed by LPCVD deposition of polysilicon over a thermally grown Si02 gate oxide which lies directly on the channel region of the silicon substrate. Pressure and temperature play key roles in determining the grain size of the polysilicon during deposition. Grain size can effect the conduction ability of the gate as well as it's ability to hold and activate dopant within the gate and not allowing it to segregate and pile up at or in the oxide.
After formation of the gates stack photoresist is spun on (likely with an anti-reflective component at some point)and patterned. The alignment and control of critical dimensions at gate poly is one of the most critical photo steps of the entire process, for CMOS logic at least. Alignment control on the order of less than 3nm of overlay tolerance is not unheard of. After litho the gate stack is etched using reactive ion etching to achieve very anisotropic profiles. At this point in modern self aligned CMOS the source/drain extension regions will be formed by ion implantation. Since PMOS and NMOS transistors obviously require different species to be implanted an additional 1 or 2 lithography steps will mask off either the NMOS or PMOS while the other is implanted at a fairly light dose. The gate stack itself serves to provide a mask over the channel region preventing the implanted dopants from reaching it. Thus the reason the process is called self aligned, rather than relying on an aligned layer of resist we can use the gate itself.
Following formation of the SDE (also called LDD, although that moniker is not correct considering the level of dopant we are putting in today?s devices) LPCVD silicon nitride is deposited conformaly. This nitride is etched in an extremely anisotropic dry etch which only attacks horizontal surfaces resulting in the rectangular gate having sidewalls consisting of nitride. This step is usually referred to as spacer etch and is very critical as it will define the actual physical dimensions of the source drain extensions. Again the wafer is ion implanted and again the PMOS devices are separated from the NMOS through lithography patterning. This time the dose implanted is extremely heavy, the heaviest throughout the entire fabrication process. Having heavily doped silicon for your source/drain is important as the resistivity of silicon is reduced as dopant levels increase. You don't want your transistor switching speed limited by the R inherent in your source/drain. At the same time as the dopants are forming the source/drain they are being stopped from going into the channel by the gate again. This step is very critical though as we want those dopants to also dope our gate very heavily to result in a fairly good conductor. The exact dose delivered also has to provide a profile which will tailor the fermi potential of the gate to lead to optimal balance in the operation between the nmos and pmos devices (i.e. pmos Vt = -1v, nmos Vt = 1v). The only way to achieve this without degrading your channel mobility with excessive Vt adjust implants is to dope the PMOS gates with a p-type dopant (B) and the NMOS gates with a n-type dopant (As, P).
After implantation a blanket layer of cobalt is deposited onto the wafer. When heated through rapid thermal anneal (basically flash lamps) the cobalt will react to form CoSi and CoSi2. Remember that we still have our nitride spacers in place and Co will not react with the nitride. This prevents the gate silicide from shorting to the source/drain silicide. We call this process material salicide which stands for self-aligned silicide. As other posters mentioned the salicide serves to greatly reduce the contact resistance of the source/drain as eventually we will have to land metal contacts onto these to form electrical connections. The salicide also has a much lower sheet resistance than the poly gates important since some poly lines serve as the gates for multiple transistors and must make relatively long runs, R is a function of length (R=rho*length/area).
So now that we understand how a gate is formed today, let's talk about what we will be doing tomorrow. First the silicon dioxide layer that serves as the insulation between the gate and the channel of the silicon substrate. As you reduce the size of your transistors you end up requiring a strong vertical electric field to adequately control the channel. If you don't have sufficient control you will end up with problems such as not being able to ever shut off your NMOS transistors. To increase this control there are several factors which process designers can play with, but the one with the most direct impact is to reduce the thickness of the gate oxide. Control of an electric field is really nothing more than the formation of a capacitor with the two conductors being the gate itself and the silicon substrate and the insulator being the oxide. Remembering back to basic electronic theory capacitance is inversely proportional to the thickness of the dielectric between your conductive plates. So we reduce the oxide thickness, and we have done so since the beginning of MOSFET processing. Today however we are down to thicknesses less than 20 angstroms, which represent only about 4-5 atomic layers of SiO2. At this thickness there are quantum effects which cause electrons to be able to transverse the physical barrier of the oxide and travel without much hindrance from the channel to gate. If this happens we have high gate leakage and have lost the ability to shut off our transistors. We've tried to make our oxides better quality to prevent this through the reduction of contaminants and some additional tricks like nitridizing the oxide. However silicon dioxide simply will no longer serve its purpose in the future as we continue to shrink. So we need to replace SiO2 with a material that has a higher dielectric constant. If it has a higher constant that means we can use greater thickness of the material and still have the same electrical properties as a thin layer of oxide. Oxide was nice since we could just heat the wafers in an oxygen ambient environment to form it. These new 'high-k dielectrics' will have to be deposited. Likely by atomic layer deposition, ALD. The leading candidate in terms of compatibility with silicon and processing ease is hafnium dioxide. It?s still unclear whether we will put down a thin SiO2 layer between the substrate and the hafnium.
Next there is the gate material itself. With each generation it is necessary to implant a greater and greater concentration of dopant into the gate in order to reduce it?s resistivity and optimize it?s electrical characteristics. Since we are using a silicide to basically turn the polysilicon into a sort of metal itself we think to ourselves, why not just use some form of metal in the first place. It?s easy finding a metal with good conductivity. The hard part goes back to what I said about having to match Fermi work functions to match both the NMOS and PMOS transistors. A material which could serve as a gate material for both is known as a mid-band gate material. The only mid-band materials that have been found aren?t very easy to integrate into our processes. And since from the small portion of the process I outlined above you can see our process is complicated enough as it is we would like to find something simple. So it?s looking more and more likely that we will have to use 2 separate metals, one for the PMOS gates and one for the NMOS gates. Intel?s press releases simply states that they feel they have found compatible materials which they feel they can integrate into their process to serve these roles at the 45nm node.
Sorry for the length of the post, I just thought it might help some people who don?t really have a strong process background to understand what is going on and how it relates to the issues being discussed here.
-Not speaking for any company
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