Poll: Who is more popular to bash these days: 3dfx or Intel?

[PCResources]

<< Now that I've attempted to cover my rear by claiming ignorance, to actually answer the question: yes, I think it is a viable solution from an engineering standpoint, but probably not from a commercial standpoint. 64-bit SDRAM memory controllers have been done on a CPU. DDR is an extension of that involving signalling changes and tighter timing. A 128-bit SDRAM controller could be done if you combined two separate SDRAM controllers driving separate busses. But you'd practically double your CPU's pin-out (well, not quite, but close enough) by doubling the address bits and the data bits. This would increase cost substantially and dramatically increase the cost of the motherboard due to routing changes. I really don't think that this would be a commercially viable outside of a server implementation. >>



Thank you for your answer, i have been led to believe, from this and your previous posts that you are a smart and well informed person. However, i know that the implementation of 128bit regular SDRAM has already been made, but to implement it DDR, well, i would say that this would require more than implementing a 8 channel 1Ghz (128bit) RB solution, what is your take on that?


Patrick Palm

Am speaking for PC Resources

 

[pm]

Well, I did say that I don't know memory very well... Ask me CPU questions and I'm on more comfortable ground.

What chipset has a 128bit PC133 SDRAM controller?

Since I got the first answer wrong, I think I'll quit while I'm behind. I can't comment on the DDR vs. Direct RDRAM because I really don't know what I'm talking about.

 

[PCResources]

<< What chipset has a 128bit PC133 SDRAM controller? >>



The chipset used with the SGI Zx10 VE does.

In what way were you wrong about your first answer? I think that the implementation of DDR SDRAM would be very hard, but i'm willing to change my opinion if i someone can convince me.

As for a CPU question, do you believe that the impact of RB latency can be significantly lowered by integrating the memory controller with the CPU chip? And if so, could the same thing be done with SDRAM (DDR and DDR-II) in your own opinion?

Patrick Palm

Am speaking for PC Resources

 

[pm]

How was I wrong...? Well now that I know the chipset, maybe I wasn't.

But I said that a 128bit SDRAM controller would be so costly to implement that it would be commercially unviable due to cost. And you replied that there is such a beast. And so I replied that I was wrong, since if someone is building it then it must be commercially viable. But perhaps I could still be right, since a.) SGI has been known to create products that are commercially unviable due to cost, and b.) it's a workstation product and so cost is less relevant than in a more mainstream design.

Let me think some more on the SDRAM vs. RDRAM implementation question. There's some people at work I can talk to.

 

[PCResources]

PM, i do agree, SGI's prodoucts are real expensive, but i do deal with these kinds of products every day, so i guess not knowing about this in the first place was a mistake i made.

Thank you for taking the time to ask around about this.

Patrick Palm

Am speaking for PC Resources

 

[pm]

Out of the depths, it rises... and I'm sorry for it. But I did say that I'd look into it.

I emailed three engineers that I know - one that worked on i840 (Carmel) and two that are working on future (unreleased) chipsets. The general consensus that I got from these guys is that a hypothetical 128-bit DDR-SDRAM interface would be easier to design than an 8-channel 1GHz Direct RDRAM interface. There was quite a bit of discussion - none of which which they were comfortable having posted to a public forum, there are CNDA issues involved - but this was the essential conclusion. In fact, the consensus was hands-down the DDR interface would be both easier and cheaper. If you want specific reasons why, I can post some of them in a summary form (but the emails are at work, and I'm at home right now).

None of us had much of an idea which would perform the best (we design high-speed circuits, and are pretty low-level engineers for system-level performance estimation), but we guessed that it would almost certainly be the Rambus interface - although this would depend strongly on the application and the compiler optimizations.

 

[PCResources]

PM:

I do believe that you might be right, but there are some finer points to this issue that i would like to add. The difference between making a 128bit wide RB interface lies within the actual memory interface. As for the signalling, it would be a lot easier to make (with RB) as it is a packeted transfer.


I would like to ask why they think that this would be such a hard solution, as an EE myself, i understand the thinking about these to memory configs and i cannot say that i believe that they are correct.

Would you accept a e-mail from me, in wich i describe my standpoint on a 128bit wide DDR more technically?

Patrick Palm

Am speaking for PC Resources