Please tell me how the different "bus speeds" interact

[Southpaw]

Hey All,

Can someone point me to (or explain) how the different bus speeds/caches interact...

ie...I have an Iwill KK266...

where does the actual 266 actually interact?
what about the DramClk of 133? any place else besides the Dram??
What about the Cache speeds for L1 & L2?

A block diagram would be excellent..

thanks

Southpaw

 

[AndyHui]

Both the L1 and L2 cache speed are running at the same speed of the processor, and effectively independent of the Front Side Bus speed.

The actual FSB on an AMD system is either 100MHz or 133MHz. In your case it is 133MHz. AMD processors use Double Data Rate, sending data on the rising and falling edge of the clock signal, to get the effective 266MHz.

From the FSB, we get the DRAM clock, the PCI bus speed and the AGP bus speed.

At 133MHz, the PCI bus is set to 1/4 of the FSB (33MHz) and the AGP at 1/2 the FSB (66MHz).

DRAM clock can be set by the BIOS to run synchronously with the FSB, ie running at 133MHz when the FSB is at 133MHz, or asynchronously: 100MHz with the FSB at 133MHz.

 

[Southpaw]

Andy,

thx...that was exactly what I needed...Nice and cocise also...

I left a rating also...

thx

Southpaw