Please help me understand llano and sandy bridge

[Terzo]

I had the upgrade itch some time ago and while my system isn't new, its performance is sufficient. I promised myself I could upgrade when the llano and sandy bridge architectures are released. In light of that I have been getting quite excited about them, though there are some questions I have.

Regarding sandy bridge, here is what I currently understand, so correct me if I'm wrong:
-is a "tock" and will be intel's second 32nm architecture
-related to being a tock, it is a completely new architecture, rather than being a clarkdale derivative
-unlike clarkdale, the integrated graphics will be on die
-the igp is dx10 based
-release date of q4 2010? or q1 2011?

As for llano...
-will be a 32 nm architecture? or 45nm?
-seems to be a derivative of the phenom II, albeit with no l3 cache ala the athlon II
-is amd's first cpu with a gpu, which will be on die
-the igp is dx11 based and rumored to be equivalent to the 5570
-release date q1 2011?

From what I've read so far (not that I deeply understand processors), it sounds like intel will likely have better performance, but amd's on die gpu will be superior to the intel version.

I have a couple of questions. First, what is the expected performance of the intel igp? I'm assuming it wont touch the amd, but will it be better than the clarkdales? Twice as good?
Second, are the release dates just guesses? Originally I was expecting both Q1 2011, but then I've read that intel (and maybe even amd) could be out late 2010, or as late a q2 2011 (mainly amd). I'd love a holiday release but dont want to get my hopes up.

Really I'm especially excited by the prospects of the amd gpu, since if the rumors are true I feel like it would suffice for most games, which would be pretty damn sweet.

Are you guys looking forward to either release, or planning to sit out this next generation and upgrade with the next?

 

[Idontcare]

-will be a 32 nm architecture? or 45nm?

llano will be 32nm SOI HKMG.

There is some confusion right now as to what exactly a rumored TSMC 40nm bulk-Si SION-gate "Fusion" part is going to entail. (not to be confused with llano)

My own personal opinion on this is that Bobcat will have a fusion derivative and it is Bobcat fusion that is this mystery 40nm TSMC part.

From what I've read so far (not that I deeply understand processors), it sounds like intel will likely have better performance, but amd's on die gpu will be superior to the intel version.

You really have to breakdown your expectations and pre-assessments of these products into two buckets of computational uses.

Traditional/Classical compute (cpu for cpu stuff, gpu for graphics-specific stuff) versus Evolutionary/Revolutionary ISA changes (AVX in Sandy, APU's in Llano).

For your traditional cpu compute stuff - running existing desktop apps and software programs - the Sandy chip will undoubtedly have the upperhand when it comes to IPC unless Intel seriously borks the microarchitecture and does a P3 -> Willamette part deux.

(yes Llano cpu cores are expected to be mostly nothing more than 4rd gen K10 architecture, expect some improvements naturally but nothing absurd)

For your traditional gpu stuff - playing games and watching videos - expect the Llano chip to smack Sandy around as if it were 2 months late on rent.

Where the wild cards come into play is recompiled desktop apps - the AVX ISA enhancements coming with Sandy hold promise to really boost the IPC and its pretty much a complete mystery at this point as to just how much the APU's on Llano can be leveraged into performance gains (but that is the plan and has been the plan for four years now so one should comfortable in assuming AMD has planned well ahead to enable compilers to leverage this asset).

 

[Martimus]

I can answer the Llano questions, as I don't know much about the initial SB, other than it will be the low end model.

As for llano...
-will be a 32 nm architecture? or 45nm?
-seems to be a derivative of the phenom II, albeit with no l3 cache ala the athlon II
-is amd's first cpu with a gpu, which will be on die
-the igp is dx11 based and rumored to be equivalent to the 5570
-release date q1 2011?

From what I've read so far (not that I deeply understand processors), it sounds like intel will likely have better performance, but amd's on die gpu will be superior to the intel version.

Are you guys looking forward to either release, or planning to sit out this next generation and upgrade with the next?

Llano will infact be on the 32nm process, and is scheduled to ship this year, although I wouldn't expect volume until next year. It is very low power (20-59W), and as such it appears to be targeted at lap-tops. It does have Phenom II architecture, with power gating and a turbo mode that should be better than Thuban due to the power gating. Also the cores have at least 1MB of L2 cache each, vs. 512kB of cache on the Athlon II.

The initial cropped pictures of the die appear to show 6 sets of 80 SP's or 480 SP's. The larger die shot actually looks like 12 sets, or 960 SP's but I really doubt that number as that would be more than the 4870. It will be a DX11 part. It will be on a new socket, and is rumored to be featured on the next MacBook.

I wouldn't expect it to have a lot of processing power, and I would mostly consider it in a laptop over a desk top. Bulldozer is the actual next generation CPU from AMD, and that isn't expected until 2H 2011.

AMD Roadmap as of Dec 2009

Llano full die shot

 

[Martimus]

llano will be 32nm SOI HKMG.

There is some confusion right now as to what exactly a rumored TSMC 40nm bulk-Si SION-gate "Fusion" part is going to entail. (not to be confused with llano)

My own personal opinion on this is that Bobcat will have a fusion derivative and it is Bobcat fusion that is this mystery 40nm TSMC part.

That would be my guess as well. Since Bobcat was supposed to be designed for the bulk process, and it does have an integrated GPU.

 

[Terzo]

Thanks for the answers so far.

Where the wild cards come into play is recompiled desktop apps - the AVX ISA enhancements coming with Sandy hold promise to really boost the IPC and its pretty much a complete mystery at this point as to just how much the APU's on Llano can be leveraged into performance gains (but that is the plan and has been the plan for four years now so one should comfortable in assuming AMD has planned well ahead to enable compilers to leverage this asset).

The traditional uses is easy enough to understand, but this section goes over my head. What are these AVX ISAs, and is the APU the technical term for the included gpu?

I can answer the Llano questions, as I don't know much about the initial SB, other than it will be the low end model.


Llano will infact be on the 32nm process, and is scheduled to ship this year, although I wouldn't expect volume until next year. It is very low power (15W-30W IIRC), and as such it appears to be targeted at lap-tops. It does have Phenom II architecture, with power gating and a turbo mode that should be better than Thuban due to the power gating. Also the cores have at least 1MB of L2 cache each, vs. 512kB of cache on the Athlon II.

So is llano laptop only? Or is that you don't think the desktop variants will be available until 2011?

 

[Martimus]

Thanks for the answers so far.

So is llano laptop only? Or is that you don't think the desktop variants will be available until 2011?

I really don't know. Just seeing the low TDP numbers makes me believe this chip is focused on the mobile market. I do expect desktop variants to be released, but seeing the TDP rumors, I wouldn't be surprised if it starts out as a laptop only part.

EDIT: I found the TDP: http://huskyshardware.com/amd-ships...ers-plans-to-initiate-production-in-late-2010
20W - 59W, so the upper end appears to be into the normal realm of desktop CPU's, or at least for low power versions.

 

[Idontcare]

The traditional uses is easy enough to understand, but this section goes over my head. What are these AVX ISAs, and is the APU the technical term for the included gpu?

AVX from the horse's mouth:

Intel AVX is a new 256-bit SIMD FP vector extension of Intel Architecture. Its introduction is targeted for the Sandy Bridge processor family in the 2010 timeframe. Intel AVX accelerates the trends towards FP intensive computation in general purpose applications like image, video, and audio processing, engineering applications such as 3D modeling and analysis, scientific simulation, and financial analytics.

Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture. The main elements of Intel AVX are:

• Support for wider vector data (up to 256-bit).
• Efficient instruction encoding scheme that supports 3 and 4 operand instruction syntax.
• Flexibility in programming environment, ranging from branch handling to relaxed memory alignment requirements.
• New data manipulation and arithmetic compute primitives, including Broadcast, permute, fused-multiply-add, etc.

While any application making heavy use of floating-point or integer SIMD can use Intel AVX, the applications that show the best benefit are those that are strongly floating-point compute intensive and can be vectorized. Example applications include audio processing and audio codecs, image and video editing applications, financial services analysis and modeling software, and manufacturing and engineering software.

APU from the horse's mouth:

What is an Accelerated Processing Unit?​

At the most basic level, AMD’s new Accelerated
Processing Units combine general-purpose x86 CPU
cores with programmable vector processing engines on
a single silicon die. AMD’s APUs also include a variety of
critical system elements, including memory controllers,
I/O controllers, specialized video decoders, display
outputs, and bus interfaces, but real appeal of these
chips stems from the inclusion of both scalar and vector
hardware as full-fledged processing elements. Others
have lashed a CPU and a basic graphics unit together in
a single package, but none have attempted this feat with
truly programmable GPUs like those in the AMD Fusion
designs, let alone GPUs that can be programmed using
high-level industry-standard tools like DirectCompute and​

OpenCL.

What can APUs do for traditional workloads?​

Although it’s exciting to look at the new applications that
will finally become practical in the “Fusion” era, the fact
remains that most users will want their new APU-based
systems to handle a mix of traditional applications for
office productivity and Internet access, along with those
new exciting apps. Fortunately, the changes AMD made
to enable new APU-accelerated applications can also​

help existing applications run better as well.

 

[Martimus]

The initial cropped pictures of the die appear to show 6 sets of 80 SP's or 480 SP's. The larger die shot actually looks like 12 sets, or 960 SP's but I really doubt that number as that would be more than the 4870.

Llano full die shot

Actually, looking at that die picture again, it looks like 18 blocks of SP's, not 12. I have a hard time believing there would be 1440 SP's on the Llano, as it would be horridly bandwidth starved. Maybe each block is smaller than 80SP's? (I could see 40SP's and 720 Stream Processors, but that is pure conjecture.)

 

[Idontcare]

Actually, looking at that die picture again, it looks like 18 blocks of SP's, not 12. I have a hard time believing there would be 1440 SP's on the Llano, as it would be horridly bandwidth starved. Maybe each block is smaller than 80SP's? (I could see 40SP's and 720 Stream Processors, but that is pure conjecture.)

Martimus as memory serves that die-shot you are looking is a truncated version...the bottom portion of the full dieshot is cropped off.

There was a thread, either at Aces or XS, in which Hans and some other guys realized that the full dieshot of Llano had actually been previously shown in public by way of some marketing materials which contained a full Llano dieshot in the background.

I'll see if I can locate that thread and the full diemap.

 

[Idontcare]

Found the post I was thinking of: http://www.xtremesystems.org/forums/showpost.php?p=4106296&postcount=18

looks like you did too (same diemap as you have been using)

here's more Llano goodness with Hans and Dresdenboy:
http://www.xtremesystems.org/forums/showthread.php?t=250241

http://www.xtremesystems.org/forums/showthread.php?t=244887

Actually, looking at that die picture again, it looks like 18 blocks of SP's, not 12. I have a hard time believing there would be 1440 SP's on the Llano, as it would be horridly bandwidth starved. Maybe each block is smaller than 80SP's? (I could see 40SP's and 720 Stream Processors, but that is pure conjecture.)

Bandwidth starved if the SP's are running at high clocks...maybe they are going low clockspeed route with the GPU silicon side of things to keep TDP in check for mobile reasons (as well as powergating SP's). Power goes as Vcc cubed but GHz goes as Vcc...for highly parallel workloads it makes sense to lower Vcc and GHz while adding more SP's.

 

[beginner99]

AVX from the horse's mouth:

So AVX is basically a response to gpgpu?

WHat was already mentioned is that the useful version of sandybridge ("enthusiats platform") will appear in Q3 2011. Anything before is a crippled consumer version. Search this forum. There is a thread about this.
Crippled really means crippled. P55 is ultra cool compared to it.

 

[Martimus]

Bandwidth starved if the SP's are running at high clocks...maybe they are going low clockspeed route with the GPU silicon side of things to keep TDP in check for mobile reasons (as well as powergating SP's). Power goes as Vcc cubed but GHz goes as Vcc...for highly parallel workloads it makes sense to lower Vcc and GHz while adding more SP's.

That is a good point. Llano is supposed to run between 0.8V – 1.3V, and only run 20-59W, so it makes sense that AMD did whatever they could to cut power. Since the Stream Processors take up such a small footprint, I can see why they would just put a lot of them on there and have slow clocks.

 

[IntelUser2000]

Maybe each block is smaller than 80SP's? (I could see 40SP's and 720 Stream Processors, but that is pure conjecture.)

Remember, they also need texture units.