Pipelined and non pipelined processors

[delon]

How the CPI differs between pipelined and non pipelined processors?

 

[Ken g6]

OK, I saw you in the programming forum, so I know you're trying to ask an earnest and intelligent question. But that's not much to go on.

This could refer to two different things. The most obvious is the difference between a processor that dedicates all its circuits to one instruction at a time, versus a processor that starts working on the next instruction (decoding it or some such) while processing or finalizing a previous instruction. The other option is that this refers to processors with multiple pipelines.

Assuming you're somewhat tech-savvy, I like this overview of processors from "antiquity" to the Pentium 4.

 

[Arachnotronic]

Are you taking a computer organization class?

 

[delon]

@Ken

I am working on a problem which involves comparing two processors- Processor X is pipelined and Y is not pipelined.
The following data are given for both processors:

1. clock frequency, 2. CPI for the ALU instructions, 3. CPI for control instruction, 4. CPI for FP instructions, 5. CPI for memory instructions

I have to find which processor will have better performance while executing a program where : 30% ALU instructions, 20% control instructions, 50% memory instructions.

This is my approach: At first for the non pipelined processor, I calculated the avg CPI. As an example if for processor Y,

1. clock frequency- 10GhZ,
2. CPI for the ALU instructions-3,
3. CPI for control instruction-4,
4. CPI for FP instructions-12,
5. CPI for memory instructions-3

then, avg CPI= .3*3 + .2*4 + .5*3 = .9+.8+1.5= 3.2; so the time for execution is: 3.2/10GHz = ... Now my confusion is, what procedure should I follow for the PIPELINED processor X? There is no information about the stages of pipeline.

Should I follow the same way- find the avg. cpi and then divide it with the clk frequency to find out the execution time?

 

[Tuna-Fish]

Should I follow the same way- find the avg. cpi and then divide it with the clk frequency to find out the execution time?

No. There is insufficient data to give a definitive answer -- however, the basic premise of (non-superscalar) pipelined processors is that they load a new instruction every cycle, executing multiple instructions simultaneously at the different parts of the pipeline, and only occasionally stall waiting for data or throw away results of failed speculation. So, given nothing more than what you said, I'd say it's doing an instruction per cycle. This is of course totally wrong, but what can you do.

 

[Doublejr]

No. There is insufficient data to give a definitive answer -- however, the basic premise of (non-superscalar) pipelined processors is that they load a new instruction every cycle, executing multiple instructions simultaneously at the different parts of the pipeline, and only occasionally stall waiting for data or throw away results of failed speculation. So, given nothing more than what you said, I'd say it's doing an instruction per cycle. This is of course totally wrong, but what can you do.

Tuna is correct, there is not enough info to solve this properly for the pipelined version.

 

[delon]

So, given nothing more than what you said, I'd say it's doing an instruction per cycle. This is of course totally wrong, but what can you do.

Ya, I am also confused. No other information is given for the two processors. So the only thing that I can do is to consider that the pipelined processor is doing one instruction per cycle. But if I do this then I am ignoring it's pipelining characteristics which will lead to a wrong answer.

Any other idea?

 

[Doublejr]

Email your prof or ta and ask them to explain what they want in an answer. That is the best route, I had to do it many times to figure out my HW. Sometimes when they write questions they forget to put in enough info to solve them properly.

 

[delon]

Well, I came across a similar type of question with solution. Here it is:

Parameter
Pipelined Version - Non Pipelined Version
Clock Rate: 500 MHz - 350 MHz
CPI for ALU Instructions: 1 - 1
CPI for Control Instructions: 2 - 1
CPI for Memory Instructions:2.7 - 1

a) For a program with 20% ALU instructions, 10% control instructions and 70% memory instructions, which design will be faster? Give a quantitative CPI average for each case.

Average CPI for Pipelined Version = (0.2*1 + 0.1*2 + 0.75*2.7) = 2.29
Average CPI for Non-Pipelined Version = (0.2*1 + 0.1*1 + 0.7*1) = 1.0
CPU execution time for Pipelined version = 2.26/(500 Mhz) = 4.5ns
CPU execution time for Non-Pipelined version = 1.0/(350 Mhz) = 2.8ns
The non-pipelined version is faster.

I am lost! Any comment on this? It seems that they have disregarded pipeline for the pipelined processor.

 

[Matthiasa]

For the non-pipelined version the instruction would be able to immediately access the memory and control structures, while an instruction would have to wait for the previous instruction on a pipelines processor until it could access it. So for a single instruction the non pipeline version would execute faster(what that example actually shows the average of).

For the pipelined version you would need the number of stages in the pipeline to figure out its cpi for running multiple instructions, without it you can't answer.

 

[delon]

For the non-pipelined version the instruction would be able to immediately access the memory and control structures, while an instruction would have to wait for the previous instruction on a pipelines processor until it could access it. So for a single instruction the non pipeline version would execute faster(what that example actually shows the average of).

For the pipelined version you would need the number of stages in the pipeline to figure out its cpi for running multiple instructions, without it you can't answer.

Assuming a million of instruction how can I compare the time required to execute a program for the problem which I have mentioned earlier ? I can easily figure it out for the non pipelined processor but I'm confused about calculating the execution time for pipelined processor.

 

[Matthiasa]

You would need to know the length of the pipeline.
After knowing that it would average instruction time, minimum being the length of the pipeline as some instructions will need to stall the pipeline. It then becomes the average cycles an instruction spends in a pipeline divided by the length of the pipeline.
The reason for that is that after the instructions start being executed instructions should be exiting the pipeline one after another.
A simple example being a set of instructions that take say 5 cycles each, the pipeline is 5 stages and has been running long enough that the pipeline is full. Now for each cycle that passes an instruction is leaving the pipeline and has been fully executed, leading to an average of one instruction per cycle. It gets more complicated with branch misses and other reasons for stalling though.