Phenom II 940 now or AM3 Phenom II next month?

[SunnyD]

Originally posted by: Idontcare
Yeah I'm not asking whether increasing HT means increased L3$ or not, of course it is implied that raising one also raises the other...I was more just curious based on what you know of the architecture whether the increased HT itself is really going to contribute to IPC gains or whether it was more likely that the commensurate increases in L3$ speed would be the dominate contributor to IPC increases with AM3/DDR3 PHII's vs PHII's on AM2+/AM2.

I'm hoping I'm following your question correctly - I am not entirely certain of DDR3's gains over DDR2. I remember when DDR2 came out (PC4200?) , the first iterations came out with latencies and speeds that it really wasn't any faster than DDR-400 at the time. It was the headroom provided as the technology matured that started giving way to performance increases. I honestly don't know if DDR3 is/will follow the same pattern (to be honest, I haven't followed DDR3's development much at all - all I know is that it's supposed to be fast enough that AMD will be migrating from GDDR5 to DDR3 for video cards in the next iteration).

With that said, I've skipped a generation of AMD processors - and I honestly don't know if The Phenom II is bandwidth starved with DDR2 or not. If I would venture a guess, the faster cache and HT link itself (to ferry the data to the cache) will be more important performance-wise than DDR2/DDR3. With that said, in multi-threaded apps, I think the faster HT links and cache will make for a bit more performance with cross-core communication - especially since the Phenom II has a larger cache to deal with (more data in faster cache = less reliance on the memory bus speeds).

So in short - my opinion would be that the 11% increase in HT/Cache speed will mean more for the AM3 Denebs than DDR3 would (which would mean the AM3 Denebs in an AM2+ socket should perform better than the AM2+ Denebs do from day one by a few %).

There's so many variables (load types, etc) that I honestly would be lying if I could tell you with any certainty which means more to this CPU at this point. I am definitely no electronics engineer, but since we're talking apples-to-apples with merely a clock comparison, you can bet the AM3 version will be faster, but I doubt DDR3 will have a ton to do with it.

 

[Idontcare]

Originally posted by: SunnyD

Originally posted by: Idontcare
Yeah I'm not asking whether increasing HT means increased L3$ or not, of course it is implied that raising one also raises the other...I was more just curious based on what you know of the architecture whether the increased HT itself is really going to contribute to IPC gains or whether it was more likely that the commensurate increases in L3$ speed would be the dominate contributor to IPC increases with AM3/DDR3 PHII's vs PHII's on AM2+/AM2.

I'm hoping I'm following your question correctly - I am not entirely certain of DDR3's gains over DDR2. I remember when DDR2 came out (PC4200?) , the first iterations came out with latencies and speeds that it really wasn't any faster than DDR-400 at the time. It was the headroom provided as the technology matured that started giving way to performance increases. I honestly don't know if DDR3 is/will follow the same pattern (to be honest, I haven't followed DDR3's development much at all - all I know is that it's supposed to be fast enough that AMD will be migrating from GDDR5 to DDR3 for video cards in the next iteration).

With that said, I've skipped a generation of AMD processors - and I honestly don't know if The Phenom II is bandwidth starved with DDR2 or not. If I would venture a guess, the faster cache and HT link itself (to ferry the data to the cache) will be more important performance-wise than DDR2/DDR3. With that said, in multi-threaded apps, I think the faster HT links and cache will make for a bit more performance with cross-core communication - especially since the Phenom II has a larger cache to deal with (more data in faster cache = less reliance on the memory bus speeds).

So in short - my opinion would be that the 11% increase in HT/Cache speed will mean more for the AM3 Denebs than DDR3 would (which would mean the AM3 Denebs in an AM2+ socket should perform better than the AM2+ Denebs do from day one by a few %).

There's so many variables (load types, etc) that I honestly would be lying if I could tell you with any certainty which means more to this CPU at this point. I am definitely no electronics engineer, but since we're talking apples-to-apples with merely a clock comparison, you can bet the AM3 version will be faster, but I doubt DDR3 will have a ton to do with it.

Cool, that makes sense to me. Thanks for explaining your thoughts on it.

I was under the perception that increasing the L3$ speed alone will contribute the lionshare of the IPC improvements in AM3 platforms...but then I saw that techreport review of the i7 940 and the impact of DDR3 bandwidth versus uncore clockspeed and it proved to me that I know jacksquat about the bottlenecks in these latest generation cpu's.

So now I am hoping AM3 benches will shed some light and give me a new sense of direction of what to expect in future platform iterations.

 

[SunnyD]

Originally posted by: Idontcare
Cool, that makes sense to me. Thanks for explaining your thoughts on it.

I was under the perception that increasing the L3$ speed alone will contribute the lionshare of the IPC improvements in AM3 platforms...but then I saw that techreport review of the i7 940 and the impact of DDR3 bandwidth versus uncore clockspeed and it proved to me that I know jacksquat about the bottlenecks in these latest generation cpu's.

So now I am hoping AM3 benches will shed some light and give me a new sense of direction of what to expect in future platform iterations.

Well, the i7 being a new architecture from the ground up, it was designed around DDR3. Since DDR3 supposedly has the headroom, I would venture a guess that being able to pull data in faster with i7 (being architectured for that), these new concepts come into play. I'm not sure how efficiently Deneb is able to fill its cache in the first place, since it was never designed that way (growing off the Athlon 64, then Phenom 1). If the L3 is just an incremental "bolt-on", it may not make as much impact as i7's structure.

Be that as it may, my original question is, do I spring for a "crippled" Deneb now, or do I wait for the "full" version coming in the next month or so? Decisions decisions.

 

[nyker96]

AM3 definitely!!

 

[William Gaatjes]

Originally posted by: SunnyD

Originally posted by: Idontcare
Cool, that makes sense to me. Thanks for explaining your thoughts on it.

I was under the perception that increasing the L3$ speed alone will contribute the lionshare of the IPC improvements in AM3 platforms...but then I saw that techreport review of the i7 940 and the impact of DDR3 bandwidth versus uncore clockspeed and it proved to me that I know jacksquat about the bottlenecks in these latest generation cpu's.

So now I am hoping AM3 benches will shed some light and give me a new sense of direction of what to expect in future platform iterations.

Well, the i7 being a new architecture from the ground up, it was designed around DDR3. Since DDR3 supposedly has the headroom, I would venture a guess that being able to pull data in faster with i7 (being architectured for that), these new concepts come into play. I'm not sure how efficiently Deneb is able to fill its cache in the first place, since it was never designed that way (growing off the Athlon 64, then Phenom 1). If the L3 is just an incremental "bolt-on", it may not make as much impact as i7's structure.

Be that as it may, my original question is, do I spring for a "crippled" Deneb now, or do I wait for the "full" version coming in the next month or so? Decisions decisions.

I noticed the L3 cache of the i7 runs at a much higher clockrate when compared to the Ph2.

For the Ph2 the L3 and memory controller runs at 1,8 Ghz.

According to this article : core i7 clockspeed L3
The clockspeed of the core i7 L3 cache and memory controller increasing with the DDR3 memory clock to 3,2 ghz for ddr3 speeds of 1600Mhz , 2,66ghz for 1333 Mhz.
When compared the I7 965 runs it's memorycontroller and it's L3 cache 1,4 Ghz higher then Ph2.

I feel both architectures love memory bandwidth because they need a huge L3 cache, and i wonder if the Ph2 really is gasping for bandwidth. I am not sure it is save to say that when the L3 cache clock increases from the Ph2 and the Ph2 get's a lot faster then the bandwidth increase from DDR3 to DDR2 would not just be seen in synthetic benchmark but would actually make a difference. I think DDR3 at 1600 Mhz would be a good start for minimum but... Maybe the Ph2 is more latency sensitive because it's prefetchers are not anyware as good as the prefetchers i7 has or the penryns have. When you have good performing prefetchers, bandwidth is more important then latency because the prefetchers hide the latency. Because of the prefetchers, all the data always seem to be in the cache when it's needed. If the Ph2 is more latency sensitive, in this case DDR2 >>DDR3 should not make such a difference and it will all come down to a faster L3 cache.

What do you guys think, i am digging mostly from memory here.

 

[BLaber]

Phenom II's ht link can only run as fast as the NB (uncore part) speed and not above it.Also AM3 Phenom II's have their NB set to 2.0Ghz , where as AM2 Phenom II's have their NB set to 1.8Ghz , a very little bump in Nb speed , but any thing higher is better.