Pentium Processor Clock Design

[coolgirl123]

Hello friends ( Joined this forum yesterday only )


I am working on project "Pentium processor Clock design "


I have covered almost all parts or aspects of it but there are few
things which are still vague . I would like to discuss them with you


a) Which is the best or latest methodology for minimizing skew of
clock , i found some on Internet but they are old 1 .

b) Well this statement is beyond my reach


" To ensure a 1:1 relationship between the amplitude of the input
jitter and the internal and external clocks , the jitter frequency
spectrum should not have any power spectrum peaking between 500 KHz and
1/3 of the CLK operating frequency "


I worked on the statement but i found my observations contradictory ,
please explain or give me some hints about it


c ) Though there are many PLL Clock drivers but i would like to know
which is best and on the which grounds we rank PLL Clock Drivers


d ) I studied that because of high speed design picture changes but i
want to know what happens to load characteristics . I Couldn't find
any literature regarding it .


Well I would ask more question as soon as i make more progress in my
project


Thanks

 

[TuxDave]

b) Well this statement is beyond my reach


" To ensure a 1:1 relationship between the amplitude of the input
jitter and the internal and external clocks , the jitter frequency
spectrum should not have any power spectrum peaking between 500 KHz and
1/3 of the CLK operating frequency "

I'm a little lost why they brought up 500KHz. Was this from some paper?

I worked on the statement but i found my observations contradictory ,
please explain or give me some hints about it


c ) Though there are many PLL Clock drivers but i would like to know
which is best and on the which grounds we rank PLL Clock Drivers

They're usually ranked by jitter, power, and capture range. So it'll have noise transfer functions from input to output and supply to output etc...

 

[CTho9305]

a) Which is the best or latest methodology for minimizing skew of
clock , i found some on Internet but they are old 1 .

See if you can find ISSCC papers on recent Itaniums.

 

[coolgirl123]

Can you please explain it

" To ensure a 1:1 relationship between the amplitude of the input
jitter and the internal and external clocks , the jitter frequency
spectrum should not have any power spectrum peaking between 500 KHz and
1/3 of the CLK operating frequency "

 

[TuxDave]

Originally posted by: coolgirl123
Can you please explain it

" To ensure a 1:1 relationship between the amplitude of the input
jitter and the internal and external clocks , the jitter frequency
spectrum should not have any power spectrum peaking between 500 KHz and
1/3 of the CLK operating frequency "

Can you cite the source? It's a little confusing when taken out of context. Is it referring to the noise (jitter) transfer function of a pll to the output?