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Hip Hardware has posted an article on the upcoming PCI-X standard. Here's a blurb from the article:
PCI-X uses what is called ?Register-to-Register? protocol. The Sender, just as before, sends the signal to whichever Receiver it needs to communicate with. Once it has propagated across the bus, the signal is sent to a register (flip-flop circuit) that holds the signal until it is needed in the next cycle. By doing this, the Receiver has an entire clock cycle to decode the signal, and respond accordingly. On the third cycle, the Receiver responds to the Sender and the data transaction can take place. In other words, if there is a transaction that takes 20 cycles on the current PCI bus, it will take 21 on the PCI-X bus, as it needs the extra cycle to decode the logic.
Now you?re probably thinking that this will cause it to run slower because it?s taking an extra cycle. But we?re not running at 33 MHz, we?re running at 133 MHz; 4 times faster than the old PCI bus with the same amount of data integrity. It takes a 33 MHz bus 600 nanoseconds to complete 20 cycles. The 133 MHz PCI-X bus takes 150 nanoseconds to complete the same amount of cycles. Even at 66 MHz, it finishes the task in 300 nanoseconds, and with twice the data integrity of the conventional 66 MHz PCI bus.
Link to the article at Hip Hardware...
1066 Mb/s for PCIX 1.0 !!!! Just imagine AGPX....
Hip Hardware has posted an article on the upcoming PCI-X standard. Here's a blurb from the article:
PCI-X uses what is called ?Register-to-Register? protocol. The Sender, just as before, sends the signal to whichever Receiver it needs to communicate with. Once it has propagated across the bus, the signal is sent to a register (flip-flop circuit) that holds the signal until it is needed in the next cycle. By doing this, the Receiver has an entire clock cycle to decode the signal, and respond accordingly. On the third cycle, the Receiver responds to the Sender and the data transaction can take place. In other words, if there is a transaction that takes 20 cycles on the current PCI bus, it will take 21 on the PCI-X bus, as it needs the extra cycle to decode the logic.
Now you?re probably thinking that this will cause it to run slower because it?s taking an extra cycle. But we?re not running at 33 MHz, we?re running at 133 MHz; 4 times faster than the old PCI bus with the same amount of data integrity. It takes a 33 MHz bus 600 nanoseconds to complete 20 cycles. The 133 MHz PCI-X bus takes 150 nanoseconds to complete the same amount of cycles. Even at 66 MHz, it finishes the task in 300 nanoseconds, and with twice the data integrity of the conventional 66 MHz PCI bus.
Link to the article at Hip Hardware...
1066 Mb/s for PCIX 1.0 !!!! Just imagine AGPX....
