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[pcgamesn] AMD is giving Threadripper 2 moar cores and a top TDP of 250W

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DuronBurgerMan

Junior Member
Mar 13, 2017
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To be perfectly honest, I do :(
Or at least it wouldn't surprise me one bit.

AMD still operates on a shoe string budget and they're juicing the existing designs all of their worth, as they should. However, time to time they go too far with doing so, in my opinion.
I got to thinking about this, and I wonder if refresh X399 boards will allow for 8-channel instead of 4-channel. And if AMD is preserving backward compatibility by allowing the extra two dies' memory controllers to be disabled on older X399 boards to meet a 4-channel configuration. Also, wouldn't be a problem for 16 core or less TR2s, as I understand those will still be 2-die, not 4-die like the 24 and 32 core variants.

That would make more sense. If the socket can handle it, and the package can handle it - it would just be a board refresh.
 

moonbogg

Diamond Member
Jan 8, 2011
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When Threadripper came to market, I remember thinking the socket was too big and looked silly. I even called it a lunchbox lid. Well, looks like Intel is coming out with their very own lunchbox lid too, right? That's funny. I thought that was kind of ironic, unexpected, and funny.
 

beginner99

Diamond Member
Jun 2, 2009
4,721
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I got to thinking about this, and I wonder if refresh X399 boards will allow for 8-channel instead of 4-channel. And if AMD is preserving backward compatibility by allowing the extra two dies' memory controllers to be disabled on older X399 boards to meet a 4-channel configuration. Also, wouldn't be a problem for 16 core or less TR2s, as I understand those will still be 2-die, not 4-die like the 24 and 32 core variants.

That would make more sense. If the socket can handle it, and the package can handle it - it would just be a board refresh.
But then new boards would not support the old chips and vice-versa. Plus TR will eat into epyc sales. The 4x 1 channel config would be nice but I doubt it as well simply because that way they could not use chips with a broken memory controller. With 2 leech dies, they can up their yields by using such with broken memory controller or broken PCIe.
 
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wahdangun

Golden Member
Feb 3, 2011
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BTW, all of this hardware runs 24/7 to try and cure cancer in DC world. I HAVE cancer, and in the next couple of months I will loose my bladder to it, I just found out today,

So all of my expenditures have a real reason for me spending insane amounts on hardware. Feel free to contribute here: https://foldingathome.org/

Sorry for the OT,.
wtf man, I'm sorry to hear that. my mother got cancer too, so i know what you feel. and after knowing your motivation, its make me sad.

btw what breakthrough DC bring in folding@home ? sorry if i'm doubt you, so i want to know if i want to join for the cause.
 

DuronBurgerMan

Junior Member
Mar 13, 2017
21
19
41
But then new boards would not support the old chips and vice-versa. Plus TR will eat into epyc sales. The 4x 1 channel config would be nice but I doubt it as well simply because that way they could not use chips with a broken memory controller. With 2 leech dies, they can up their yields by using such with broken memory controller or broken PCIe.
Not necessarily. Perhaps it could be setup to enable only two memory controllers on older boards, and all four on a newer board that's setup for it. I mean, TheStilt could probably tell us more definitively if that's really possible, but still... I wonder.

As to the leech dies... how many "top 5%" Zen+ dies really have broken memory controllers? Serious question, does anybody know? I suspect (but don't know) that number would be very small. So I'm not sure they'd be gaining a lot of yield by doing that.

And I wouldn't worry too much about Epyc sales. TR's higher clocks and higher TDP make it less attractive for the types of uses Epyc usually sees. Furthermore, TR is single socket only.
 

The Stilt

Golden Member
Dec 5, 2015
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Not necessarily. Perhaps it could be setup to enable only two memory controllers on older boards, and all four on a newer board that's setup for it. I mean, TheStilt could probably tell us more definitively if that's really possible, but still... I wonder.

As to the leech dies... how many "top 5%" Zen+ dies really have broken memory controllers? Serious question, does anybody know? I suspect (but don't know) that number would be very small. So I'm not sure they'd be gaining a lot of yield by doing that.

And I wouldn't worry too much about Epyc sales. TR's higher clocks and higher TDP make it less attractive for the types of uses Epyc usually sees. Furthermore, TR is single socket only.
Either it will be two dies with both of the memory channels active (leech), or all dies with one of the channels active combined to an altered package (compared to gen. 1 TRs or EPYCs). Switching between the configurations won't be possible in either case.
 

LightningZ71

Senior member
Mar 10, 2017
661
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I would imagine that making a new MCM substrate for a package that's based on each die having a single channel would not be an insurmountable task in the time it took to develop TR2. The circuit pathing in the substrate would be challenging for at least two of the dies, but, given that it's a controlled environment for them, its definitely doable.

That being said, TR is a minimum effort HEDT part. Just upclocking the IF links and DRAM controllers would accomplish a big improvement in memory latency from the leech dies without impacting game mode performance in any negative way. If your workflow is not helped by the extra cores due to the latency and bandwidth constraints of the leech die configuration, then your use case is better served by the EPYC 1P product. However, if you have a task that needs lots of cores thrown at it, but can have it's working set live in 2MB of ram, then TR2-32 core might work very well for you.

I'm still quite curious to see how well a 24 core (6 cores per die) TR2 can perform when it's allowed to run free with power and thermal constraints removed. I can easily see a situation where a well designed board and cooling system can sustain an all core dynamic (PB2) OC of 4.1+Ghz. Combined with well overclocked RAM, that could be quite a monster at its price point.
 

moonbogg

Diamond Member
Jan 8, 2011
9,937
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EK has some super nice water blocks specifically for threadripper and the fins were designed for the multi die layout of the threadripper chips. That's awesome. I just came here to say that's awesome.
 
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JoeRambo

Senior member
Jun 13, 2013
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I'm still quite curious to see how well a 24 core (6 cores per die) TR2 can perform when it's allowed to run free with power and thermal constraints removed. I can easily see a situation where a well designed board and cooling system can sustain an all core dynamic (PB2) OC of 4.1+Ghz. Combined with well overclocked RAM, that could be quite a monster at its price point.

Looking at 16 core TR testing @ Anandtech, i kinda doubt viability of such overclocks for 24 core part. 50% more cores means plenty more thermal load, probably north of 500w @ voltages required to hit 4Ghz. Imho the point of this system is cheap and energy efficient rendering box ( or mining), where one runs TR2 32C at maybe 3.0-3.6Ghz, but does so without going haywire on power.
There are plenty of such example in Xeon thread on this very forum, people are unlocking them and undervolting.
 

PeterScott

Platinum Member
Jul 7, 2017
2,605
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Some good news.(If I'm not reading it wrongly:p)
https://www.chiphell.com/thread-1885192-1-1.html

the author imply TR2 is able to OC 4.8Ghz with some acceptable/normal cooling. Stay tuned.
I think we can be fairly certain that isn't the case, and no one actually seems to be talking about TR in that thread. It's more likely speculation about about Zen 2 on 7nm, not TR2 on which is on 12nm.
 

cortexa99

Member
Jul 2, 2018
142
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I think we can be fairly certain that isn't the case, and no one actually seems to be talking about TR in that thread. It's more likely speculation about about Zen 2 on 7nm, not TR2 on which is on 12nm.
I can read Chinese. The author said the SKUs which could OC to 4.8Ghz(not mentioning 1 core or all cores) is belongs to Globalfoundries Zen+(12nm) not TSMC Zen2(7nm), but what author said is understatement overall so I have to guess what SKUs he implied. It could be 2800x, or even 2700x could have better bin in second half of 2018 that could OC higher clock.

But I have to confess it seems I get something wrong about 2800x, which I supposed to think 2800x belongs to TR2 family:( SRY. But I guess it could be related to TR2 if better binning of 12nm is real.
 

Organik

Member
Jul 15, 2018
58
2
6
Same here, I think TR 2xxx will "only" be Zen+ dies on the actual Platform.

Without having new dies, a >16 cores TR would require 4 Zepline dies. This would require a new substrate (Epyc can't be used because 8ch MC) and would limit the Zepline dies to a single MC, what would certainly have an impact on performance.

That said, because AMD will not release Epyc with Zen+ dies, could it be that they plan a X499 , 8ch MC platform for those Epyc Zen+ derivates?
Brother your taking me back to science class!
 

cortexa99

Member
Jul 2, 2018
142
186
86
4.8Ghz on GF 12nm is a pipe dream.
I think I need to clarify here. I'm not NDAer or leaking/misleading something that I don't know. I just being a translator to break language barrier between my country&other foreign countries. I repost those info from local forum to foreigners just because I trust them considering their good track record, and these might be important news to people who focus on corresponding product. But since I made a mistake that this MIGHT not related to TR2 I have to stop posting anymore in this thread, until there's some true TR2 leak/news from my country.

I did some translating work not long ago outside Anand. You can see my track record.:D
https://www.overclock.net/forum/25723175-post1586.html
https://www.overclock.net/forum/25875168-post17.html
 

Hitman928

Diamond Member
Apr 15, 2012
3,400
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I think I need to clarify here. I'm not NDAer or leaking/misleading something that I don't know. I just being a translator to break language barrier between my country&other foreign countries. I repost those info from local forum to foreigners just because I trust them considering their good track record, and these might be important news to people who focus on corresponding product. But since I made a mistake that this MIGHT not related to TR2 I have to stop posting anymore in this thread, until there's some true TR2 leak/news from my country.

I did some translating work not long ago outside Anand. You can see my track record.:D
https://www.overclock.net/forum/25723175-post1586.html
https://www.overclock.net/forum/25875168-post17.html
We appreciate you being here. I don't think anyone is trying to attack you or post negatively towards you, many just doubt that the post you are translating is anything but a made up rumor by the original poster. Time will tell, though I do doubt it as well, outside of maybe golden chips on a single core on voltages you can't run on a daily basis.
 
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StinkyPinky

Diamond Member
Jul 6, 2002
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How on earth can it get to 4.8 when the 2800x cannot even get close to that? Common sense debunks that.
 

cortexa99

Member
Jul 2, 2018
142
186
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Where are these 2800X selling? Tell us quick, before they're gone.
How on earth can it get to 4.8 when the 2800x cannot even get close to that? Common sense debunks that.
Not sure whether it is still-no-exist '2800x' or something else, all I could read from author's tone is, that better OC(or XFR?) headroom on future revision of Zen+(12nm, CPU/APU) is pretty realistic.
 
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The Stilt

Golden Member
Dec 5, 2015
1,709
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Until AMD has access to a process which does not relate to Samsung 14nm LPP, the frequencies are not going to reach significantly above the levels the R7 2700X currently ships at.
That's not an opinion, but something anyone can see by simply looking at the operating characteristics of a stock 2700X CPU.
 

cytg111

Lifer
Mar 17, 2008
15,169
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I used to lobby this forum that an i7 haswell was a safe bet for a 10-year rig cause core/hz/ipc wasnt gonna change by much in that period.
Sorry. I take that back.
 

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