PC Watch: Changes in the 14/16nm FinFET process technologies for GPUs (Japanese)

[Dresdenboy]

Hiroshige Goto wrote about FinFET process technologies being used for AMD's GPUs. As the XBox One S SoC is AMD's only 16nm (i)GPU yet, this is mostly about Polaris.

Japanese (OV):
http://pc.watch.impress.co.jp/docs/column/kaigai/1013752.html

Translated (Google sounds better than Bing here):
https://translate.google.com/transl...jp/docs/column/kaigai/1013752.html&edit-text=

Note here: Variation should be much lower with FinFET! So if we see something different with Polaris, this might be due to running the design in a range more in the right part of the chart. Variation would scale up then.

If you haven't seen it before, here is AMD's power gating grid in SR:

It's being shown in the article to show the difference of 1x metal layers between SR (28SHP) and CZ (28A). A monolithic die APU always needs a trade off between higher metal layer density (die size, power) and lower density (for performance, i.e. lower wire delays). It will be interesting to see, what they've chosen for Zen/Zeppelin and smaller/bigger APUs (RR & datacenter APU). With separate CPU/GPU dies, an optimal metal layer configuration for both might be used.

 

[PhonakV30]

Is there any relation between Wafer Yield and Frequency ?

 

[ViRGE]

Is there any relation between Wafer Yield and Frequency ?

Yes. For any given frequency, only a certain percentage of your chips will be able to run at that frequency (this is a subset of parametric yield). A chip can be rejected for this, or because it's outright physically flawed (functional yield).