paging vs segmentation

[rookie1010]

hello

what is the difference between segmentation and paging? segment is defined by the two registers(base and limit), isn't a page defined by the same registers, is that correct?

the one difference that comes to mind, is that a page does not need to be composed of contiguous memory, correct?

 

[bersl2]

Originally posted by: rookie1010
hello

what is the difference between segmentation and paging? segment is defined by the two registers(base and limit), isn't a page defined by the same registers, is that correct?

the one difference that comes to mind, is that a page does not need to be composed of contiguous memory, correct?

A location in physical memory has an address. The least significant bits that fit within the page size comprise the offset within the page, and that never changes. However, the more significant bits, which in the physical address is said to identify the frame of physical memory, are translated into a virtual address, where the more significant bits identify the page of virtual memory. The frame number and page number need not be the same; in fact, they need not even have the same number of bits of address space. The memory management unit of the processor takes care of this translation by consulting page tables within memory that map a given page to a frame (or not, if the page has been swapped to secondary storage). Don't ask me how the processor knows where in memory to find the page tables. 🙂

Memory within a single page lies within a single frame, all contiguous; however, memory in adjacent pages need not be in adjacent frames.

 

[thesix]

Add to what bersl2 said,

Segmentation introduces one more hierarchy into the translation between a virtual page and a physical memory frame.

In segmented environment, each process' address space is divided into continuous "effective segments" (0, 1, 2, ...) . A segment contains multiple pages, each page belongs to one segment.
Each "effective segment" is mapped a global "virtual segment" (system wide, not continous inside one process) through segment registers.

Each "effective address" in a process contains
1) An effective segment ID
2) Page offset, which identifies a page in the segment
3) Offset within a page.

and each process has its own set of segment registers.

When you talk about vitual memory stuff, you better specify CPU architecture, since the MMU (memory management unit) in different CPU arch functions differently.

IBM POWER chips use segmentation.

 

[Nothinman]

With all of these posts by rookie1010 I feel like we're taking some sort of test...

 

[thesix]

Nothing like a "rookie" question for sure 🙂 ( no offense to rookie1010 )

 

[CTho9305]

FWIW, what bersl2 and thesix are talking about sound very little like x86 segments, and given how rookie1010 asked the question, I think he's asking about x86. If that's the case, I'd suggest reading this article, or using google for a few seconds, then coming back with more specific questions.

Don't ask me how the processor knows where in memory to find the page tables.

On some architectures I'm familiar with, there's a processor register (page table base register) that the OS sets to point to the page table, so that the CPU can walk the page table itself when there's a TLB miss. On other architectures (e.g. MIPS), it doesn't - the CPU traps when there is a TLB miss, and the OS catches the exception, then reads the page table itself.

 

[rookie1010]

thanks for the reply, i appreciate you guys answering all my noob questions

so physical memory is divided into frames and virtual memory into pages. i guess one frame fit more than one page of memory?

can one segment can fit more than one pages? i guess the memory in a segment need not be physically contiguous?

 

[bersl2]

Originally posted by: CTho9305
FWIW, what bersl2 and thesix are talking about sound very little like x86 segments, and given how rookie1010 asked the question, I think he's asking about x86. If that's the case, I'd suggest reading this article, or using google for a few seconds, then coming back with more specific questions.

Don't ask me how the processor knows where in memory to find the page tables.

On some architectures I'm familiar with, there's a processor register (page table base register) that the OS sets to point to the page table, so that the CPU can walk the page table itself when there's a TLB miss. On other architectures (e.g. MIPS), it doesn't - the CPU traps when there is a TLB miss, and the OS catches the exception, then reads the page table itself.

I assume that the architectures that resolve TLB misses in hardware (a.k.a. x86) will define the structure of the page tables more rigidly than one that does software lookups.

Damnit! Now this discussion is really getting me curious about computer architecture again. Oh well, knowing me, I'm going to end up searching through piles of documentation, start looking at an old Linux or Minix version, maybe even start writing something incredibly basic, but then losing concentration after a few days, adding another member to the heap of interesting things I want to pursue but never follow up on, increasing my self-loathing. Again. 😀

 

[thesix]

Originally posted by: rookie1010
so physical memory is divided into frames and virtual memory into pages. i guess one frame fit more than one page of memory?

No. Frame or page are just names, their size can be different on different arch.
They usually refer to the smallest unit that can be allocated or deallocated by the OS/MMU.
In the case of "large pages", if supported by OS/HW, each "page" can contain many "frames", for example, 64K page, 16MB page, 256MB page etc.

can one segment can fit more than one pages? i guess the memory in a segment need not be physically contiguous?

In POWER ( I am not sure "segmentation" has the same meaning in x86, as someone pointed out above), each segment contains 65536 (4K) pages, or 256MB memory, and of course they're not necessarily contiguous physically.

 

[thesix]

Originally posted by: bersl2
Damnit! Now this discussion is really getting me curious about computer architecture again. Oh well, knowing me, I'm going to end up searching through piles of documentation, start looking at an old Linux or Minix version, maybe even start writing something incredibly basic, but then losing concentration after a few days, adding another member to the heap of interesting things I want to pursue but never follow up on, increasing my self-loathing. Again. 😀

So am I 😀

For SPARC, see page 455 of UltraSPARC Architecture 2005 Specification (Privileged Edition)

For POWER, see page 43 of Book III: PowerPC Operating Environment Architecture

Anyone has a link to x86/64 equivalent ?

Edit: found AMD Docs:
http://www.amd.com/us-en/Processors/Dev...hAMD/0,,30_2252_869_875%5E7044,00.html

 

[CTho9305]

I strongly suggest reading chapter 4 of the AMD64 Architecture Programmer's Manual Volume 2: System Programming for the whole story on x86 segments, and chapter 5 for the story on paging. AMD's manuals are great references.

can one segment can fit more than one pages? i guess the memory in a segment need not be physically contiguous?

In POWER ( I am not sure "segmentation" has the same meaning in x86, as someone pointed out above), each segment contains 65536 (4K) pages, or 256MB memory, and of course they're not necessarily contiguous physically.

In x86, segments are defined by the segment registers, and can have practically any size between 4KB and 4GB, and each segment can be a different size. They're contiguous virtual addresses. In 2004 I worked on some segment-related logic for a CPU. Pages on x86 are usually 4KB, but I know modern AMD processors also support larger pages.

Damnit! Now this discussion is really getting me curious about computer architecture again. Oh well, knowing me, I'm going to end up searching through piles of documentation, start looking at an old Linux or Minix version, maybe even start writing something incredibly basic, but then losing concentration after a few days, adding another member to the heap of interesting things I want to pursue but never follow up on, increasing my self-loathing. Again.

So am I

For SPARC, see page 455 of UltraSPARC Architecture 2005 Specification (Privileged Edition)

For POWER, see page 43 of Book III: PowerPC Operating Environment Architecture

Anyone has a link to x86/64 equivalent ?

See page 147 (191) of the PDF I linked to - on x86, it's apparently "CR3" that holds the page table pointer.

 

[rookie1010]

thanks for the reply

A location in physical memory has an address. The least significant bits that fit within the page size comprise the offset within the page, and that never changes. However, the more significant bits, which in the physical address is said to identify the frame of physical memory, are translated into a virtual address, where the more significant bits identify the page of virtual memory. The frame number and page number need not be the same; in fact, they need not even have the same number of bits of address space. The memory management unit of the processor takes care of this translation by consulting page tables within memory that map a given page to a frame (or not, if the page has been swapped to secondary storage). Don't ask me how the processor knows where in memory to find the page tables.

frame or page are names whch are used in the physical memory and virtual memory context?

 

[bersl2]

Originally posted by: rookie1010
thanks for the reply

A location in physical memory has an address. The least significant bits that fit within the page size comprise the offset within the page, and that never changes. However, the more significant bits, which in the physical address is said to identify the frame of physical memory, are translated into a virtual address, where the more significant bits identify the page of virtual memory. The frame number and page number need not be the same; in fact, they need not even have the same number of bits of address space. The memory management unit of the processor takes care of this translation by consulting page tables within memory that map a given page to a frame (or not, if the page has been swapped to secondary storage). Don't ask me how the processor knows where in memory to find the page tables.

frame or page are names whch are used in the physical memory and virtual memory context?

Respectively, yes. When the context between physical and virtual memory is self-evident or unimportant, "page" is sometimes used interchangeably; "frame" is used generally when a distinction between physical and virtual must or should be made.

At least, this is how I understand it.

 

[rookie1010]

thanks for the reply