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P4 Quad pumped bus question

GeoffW

Junior Member
Hi

Can anyone explain how the P4 quad pumped bus works. I can get my head around DDR busses but quad speed is puzzling me?
For example the rising clk edge must be divided into 2 phases eg For a 3V signal, clk1 is during 0 to 1.5V transition and clk2 is during 1.5V to 3V transition. Is this how it works ?, if so how does it manage to achieve all the setup and hold times for the bus devices ?

Regards Geoff
 
isnt it just the "connectin" between the cpu and northbridge which is at 400/533mhz..?

im not sure of what you are askig.....maybe its just too early hehe 😉
 
Hi
yes it is the cpu and northbridge which is at 400/533mhz (100/133 Mhz really). I wasnt looking for a highly techy answer, its just I was intrigued by how it manages to do two data transfers on each of the rising and falling Clk edges.
DDR is easy to see how it works, but quad transfer seems like black magic to me? 🙂
 
Maybe differences in the electrical current? Hell I dunno... Maybe the quad pumped bus isn't much of an advantage over a double pumped bus, which might explain why AMD CPU's stomp the begjeesus of out Intel CPU's of equal MHz.
 
Originally posted by: Jeff7181
Maybe differences in the electrical current? Hell I dunno... Maybe the quad pumped bus isn't much of an advantage over a double pumped bus, which might explain why AMD CPU's stomp the begjeesus of out Intel CPU's of equal MHz.

P4's are slower clock-for-clock because the Athlon has a higher IPC, a much more efficient and powerful FPU, and a much shorter pipeline. RAMBUS is fast because it runs on a fast bus, therefore to keep up the P4 needs a higher bus speed. 400MHz bus = PC800 RDRAM... 533MHz bus = PC1066 RDRAM because RDRAM transfers like DDR... on the rising and falling of the clock hence PC800 is 400 double pumped and PC1066 is 533 double pumped. I say double pumped because of its two transfers per clock cycle.
 
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