P4 Front Side bus speeds?? Can someon Clarify for me?

[Brian07]

I have a guy here at work that insists the P4 is running on a 400mhz front side bus. Up to this point I *thought* I was pretty clear on the P4/Rambus Architecture. Can some help with the clarification? I can't argue with him because I can't put into words what is actually going on....

Thanks!

Brian

 

[SexyK]

The P4 runs on a 100MHz FSB quad-pumped to what is essentially 400MHz. The physical bus is only 100MHz, but somehow they manage to cram 4 bits of information into each clock cycle. Much like DDR RAM and AGP4x. Hope that clears it up.

Sexy K

 

[fkloster]

P4's fsb run @ 100mhz quad pumped for an effective fsb speed of 400mhz.

 

[Noriaki]

Yup, it's a 100Mhz clock that sends 4 datas/clock, so effectively it's a 400Mhz.

 

[PHATJACK]

Posts 2 & 3 are correct. It is a 100MHz bus that is "quad pumped" to an effective 400 MHz.

 

[nyati]

The Pentium 4 Front Side Bus is actually 4 seperate 100 MHz Buses multiplexed to operate as a single bus. So it has the same bandwidth as a single 400 Mhz bus would have. The actual curcuits in the bus do operate at 100 Mhz.
So, there are 4 x 100 Mhz x 64 bit buses = 3.2 GB/Sec Bandwidth. This matches up with the Rambus dual channel which is 2 x 400 MHz x 2 (DDR) x 16 bit = 3.2 GB/sec for the RAM. (PC800 RDRAM is actually 400 MHZ DDR, not 800MHz)

Hope this clears things up a bit.

Too bad it ain't Friday

 

[thorin]

Ummm I'm not sure if nyati or I are wrong. But my understanding was that it's a single 100MHz bus transferring on both the rising and falling edges of the clock signal (effectively 200MHz) and transfering twice the data (64bits instead of 32bits) for each of those tranfers.

So it's 100MHz x 2 (Transfers per clock) x 2 (Data) = 400MHz

Thorin