Overclocking Sandy Bridge on H61 chipset? Huh?

[VirtualLarry]

I thought that wasn't possible.

But according to this, Gigabyte is including an "overclocking IC" to allow it.

http://www.gigabyte.us/press-center/news-page.aspx?nid=1038

I would like to know how that works. As far as I know, only "K" unlocked chips could overclock, and only with P67 and Z68 chips.

 

[GammaLaser]

Maybe BCLK only? It didn't say anything about core multiplier, and that is internal to the CPU...so it can't really be forced by the chipset for locked SKUs.

EDIT: Found a page here that claims a modest 6% increase, which supports that the mobo is doing a BCLK OC.

 

[Kenmitch]

I think all SB's with turbo can be bumped up by 4 multipliers. Pretty sure only on a P67 or Z68 MB tho.

 

[StrangerGuy]

Maybe BCLK only? It didn't say anything about core multiplier, and that is internal to the CPU...so it can't really be forced by the chipset for locked SKUs.

EDIT: Found a page here that claims a modest 6% increase, which supports that the mobo is doing a BCLK OC.

This is hilarious...Gigabyte is running out of gimmicks to sell that a 6% OC is now the next earth-shattering super-duper "feature".

 

[IntelEnthusiast]

I think all SB's with turbo can be bumped up by 4 multipliers. Pretty sure only on a P67 or Z68 MB tho.

I have heard that it tops out at 4 bins higher is the most that a non-"K" processor can been overclocked. This issue with Gigabyte H61 and H67 and me go a ways back on this board. So I will fall back on the Intel standard answer for this question. The only chipsets that will allow you to overclock your processor is the P67 and Z68 chipset series boards; all the others will not allow you to overclock. So how Gigabyte is doing this I don't know.

Christian Wood
Intel Enthusiast Team

 

[sm625]

I never understood how Intel could lock their clocks. It makes absolutely no sense to me because they need some kind of external reference. If you increase the BCLK then that should overclock the chip and there would be no way for the chip to reject it. And if the overclock presents a problem for the pciE bus then you run that clock through a divider to compensate. ie if your BCLK is 133MHZ you run it through a 4:3 divider and you get your 100MHz pciE clock. Sure its one more chip on your motherboard, and it might increase pciE latencies a bit, but hell there has to be a market for a SB celeron clocked at 4.2GHz, even if the pciE takes a 20% hit.

 

[Concillian]

I never understood how Intel could lock their clocks. It makes absolutely no sense to me because they need some kind of external reference. If you increase the BCLK then that should overclock the chip and there would be no way for the chip to reject it. And if the overclock presents a problem for the pciE bus then you run that clock through a divider to compensate. ie if your BCLK is 133MHZ you run it through a 4:3 divider and you get your 100MHz pciE clock. Sure its one more chip on your motherboard, and it might increase pciE latencies a bit, but hell there has to be a market for a SB celeron clocked at 4.2GHz, even if the pciE takes a 20% hit.

PCIE controller is on the chip. You can't run a 4:3 divider, you'd have to essentailly design your own chipset that had an independent PCIE controller, then communicated with the CPU via some bus that:
1) was never intended to carry PCIE data
2) has the bandwidth
3) doesn't also have problems with higher bclk.

FSB used to carry this, but it doesn't exist anymore, right?

I don't think it's as easy as you think it is.

 

[Ken g6]

You can't run a 4:3 divider

Why not? Some property of PCIE? Or does that part of the chip stop working at those high frequencies?

 

[ViRGE]

Why not? Some property of PCIE? Or does that part of the chip stop working at those high frequencies?

Well the integrated PCIe controller doesn't support 4:3 (or at least it isn't accessible). Which means you'd be running the PCIe bus at frequencies much too high; the devices attached to it would long give up, assuming the controller doesn't first. It's a bus designed to run at a very specific speed, there's not much of a margin to work with.

 

[Ken g6]

OK, I see an issue on the Wikipedia page: "PCIe sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency is still comparable to conventional PCI, which has dedicated interrupt lines."

But could you run the bus at much lower frequencies? Say 1/2 normal or a little higher? Then you could have a chip that tells the CPU all devices are PCIe-1.0a, tells the devices the CPU only accepts PCIe-2.0 devices (no PCIe 1.x allowed), and does a 1:2 multiplier/divider between them. Right?