Ever since PCs starting having 64-bit data buses with the original 66MHz Pentium, the memory controllers in many motherboard chipsets have been able to do ECC error correction using the parity bits, as long as you use parity (72-bit) rather than 64-bit non-parity DIMMs.
This is substantially cheaper than implementing the ECC logic in the DIMM. Also, the ECC logic is obviously built into the Opteron anyway because to satisfy requirements of the server market, it does ECC error correction on the L1 and L2 cache. Why can't this same ECC circuitry be used by the Opteron's internal memory controller to do error correction on normal unbuffered parity DIMMs, reducing RAM costs and more than likely improving latency?
For those that don't know, the number of "extra" bits required to do single-bit-error ECC on a block of data is n+2, where 2^n is the first power of 2 >= the number of bits in the block. So for a data bus that transfers 64-bits at a time, 8 extra bits are required for ECC, which is the exact same number required for parity with 1 parity bit per byte, and the reason that chipsets started doing this when CPUs got 64-bit busses. It wasn't doable with 486 and earlier processors with 32-bit or smaller busses, because there would normally be only 4 parity bits to 32 data bits, but you need a minimum of 7 bits to do ECC on 32 bits. If AMD was really crafty they could take advantage of the fact that the Opteron bus is actually not just 64 bits but 128 bits, which would have 16 parity bits coming from normal DIMMs when only 9 are needed for ECC on 128 bits, and use the extras for correcting some 2 and 3 bit errors on each 128-bit block rather than just single bit errors.
This is substantially cheaper than implementing the ECC logic in the DIMM. Also, the ECC logic is obviously built into the Opteron anyway because to satisfy requirements of the server market, it does ECC error correction on the L1 and L2 cache. Why can't this same ECC circuitry be used by the Opteron's internal memory controller to do error correction on normal unbuffered parity DIMMs, reducing RAM costs and more than likely improving latency?
For those that don't know, the number of "extra" bits required to do single-bit-error ECC on a block of data is n+2, where 2^n is the first power of 2 >= the number of bits in the block. So for a data bus that transfers 64-bits at a time, 8 extra bits are required for ECC, which is the exact same number required for parity with 1 parity bit per byte, and the reason that chipsets started doing this when CPUs got 64-bit busses. It wasn't doable with 486 and earlier processors with 32-bit or smaller busses, because there would normally be only 4 parity bits to 32 data bits, but you need a minimum of 7 bits to do ECC on 32 bits. If AMD was really crafty they could take advantage of the fact that the Opteron bus is actually not just 64 bits but 128 bits, which would have 16 parity bits coming from normal DIMMs when only 9 are needed for ECC on 128 bits, and use the extras for correcting some 2 and 3 bit errors on each 128-bit block rather than just single bit errors.
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