Thanks LeBlatt, very interesting reading 😎
I noted this part down as the most interesting for me:
<< Q: Will you be working further to improve the optimizations?
A: Definitely. As I said before, I've already got two more stages planned. As it is, I'm getting two or less instructions executing per clock on the Athlon core, but the processor itself can execute three. The two stages I have planned should get more towards getting three instructions per clock cycle. >>
I knew the Athlon had three integer units, and assumed that was why it's so much better at RC5 (and OGR for that matter) than the PPro line of chips (PII/PIII,Celeron(I/II)) but obviously that isn't why :Q This is very interesting since it yet again shows what a powerful chip the Athlon is, it's outproducing the PPros by a large margin, and it's still using the same amount of instructions per clock and this is only 2/3rds of the amount of instructions it can do!!! Not that I think he can increase the output by half, but it surely leaves me thinking how much more can be squeezed from these babies 😎
Don't mind me I'm just drooling over the possibillity for an increased keyrate 😉
With love and respect your fellow TA member
Two-Face