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Article OCP Bunch of Wires: A New Open Chiplets Interface For Organic Substrate


Golden Member
Nov 27, 2007
Saw a really interesting article about packaging on wikichip yesterday:

It discusses a new vendor agnostic interface of doing Multi-Chip Modules, like what AMD is doing currently with Zen2. That is without silicon-on-silicon expensive stuff like Interposers and silicon bridges.

It seems that MCM can be much further than I imagined, Here is a comparison to other technologies (including the one currently used in Zen). I suggest to read the entire article but the most interesting part was probably this table:

Screenshot 2020-01-06 at 10.34.38.png

OCP has a working prototype on GlobalFoundries 14nm process, they say that on TSMC 7nm power should be down to 0.5pJ/bit. Compared to Zen that's a 3x increase in peak data rate at nearly 4x less power per-pin.

Another really interesting part was this:
Since dies are spaced apart, a trace length of 25mm to 50mm is required with a latency of sub-5ns
Which goes to show, that chiplet-design in itself shouldn't add that much latency (something th at chiakokhua has also estimated on twitter). Using chiplets should only add ~5ns to memory latency.

Intel get's ~40ns with 9900K with highest-end tight timings while it's ~55ns at stock (2666 Mhz). Zen 3 doesn't really go below 60ns even with the most aggressive timings and on cheaper 3200Mhz/3600Mhz RAM ~70nm is common. So taking Skylake as reference 45-50ns memory latency on a future Zen architecture should be theoretically doable.

As the technology is still in the prototype phase, Zen 3 taped out last year and AMD is only an opencompute community member (compared to say Intel that is Platinum), I doubt we'll see anything like that used in Zen 3 (though one could hope). Still there is significant performance sitting on the table even for MCP.

(e.g. what was new to me)
1. MCM processors without fancy interposers/2.5D solutions still have a lot of juice left compared to what AMD has currently implemented with Zen 2.
2. Good MCM design has a smaller impact on memory latency than people think. Even with chiplets 45-50ns should be perfectly doable.


Golden Member
Nov 27, 2007
im pretty sure the 2pJ/bit for Zen is not Zen2/Rome but Zen/Naples.
Yes, probably. And I have no doubt they will improve upon that with Zen3/Milan. Still I found the article interesting to see what's already proven to be possible (even when integrating chips from GloFo 14nm process).

IMO the "Bunch of Wires" interface seems enticing because it's not proprietary unlike all of the current 2.5D/3D packaging tech (e.g you can't desing something for TSMC and later use it for Samsung, without a huge redesign).

That said, obviously it also has plenty of limitations. There are many cases where stacking your chips is the only solution, and AMD's recent patents clearly show they are also moving in that direction (probably as soon as Zen 4). Still it looks like organic substrates still have their uses


Platinum Member
Jun 1, 2017
Looks like this is WikiChip's accompanying piece to AT's interview with Intel's Ramune Nagisetty. There BoW was name dropped there as well, WikiChip's David Schor participated, and Nagisetty sounded pretty open to have open packaging and interface standards.

This is pretty exciting. Ideally AMD would jump onto this for one of the upcoming Zen gens (if only as an optional compatibility mode), allowing their CCD, IOD and whatever else dies to be using as part of custom BoW packages.
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