NVMdurance for Intel's Optane DIMMs? (Implications on performance, latency, endurance, retention)

[cbn]

As some of you may know NVMdurance has been collaborating with Intel on extending the life of NAND using machine learning and an Altera SoC FPGA. (SIDE NOTE: This was done on a PCIe Add-in-card with the Altera controller being separate from the NAND SO-DIMMs.)

And from this legitreviews post we know the Optane DIMM has a FPGA controller:

Intel stated that they are working on 128GB, 256GB and 512GB 3D XPoint NVDIMM DIMMS that are aimed for the server/enterprise market. Note the raised FPGA section in the middle of the heatsink.



Intel’s recently acquisition of Altera makes more sense now after seeing this product as Intel’s leading-edge products and manufacturing process with Altera’s leading field-programmable gate array (FPGA) technology are a pretty good fit for one another. Altera has a FPGA-based SSD controller and it will be interesting to know what Intel us using under that heat spreader.

Which I assume is following the scheme of NVDIMM-F:

We also know that Intel/Micron is capable of making 3DXpoint at least two ways:

(a high endurance layer design with slower access time vs. low endurance layer design with faster access time).

http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20160276022".PGNR.&OS=DN/20160276022&RS=DN/20160276022

Some embodiments include architectures in which two or more memory array decks are vertically stacked. One or more of the stacked decks is configured to have different operational characteristics relative to others of the stacked decks. For instance, one or more of the decks may be configured to have rapid access times suitable for utilization in XIP (execute in place) applications and/or dynamic random access memory (DRAM) emulation applications, and one or more others of the decks may be configured to have stabile, possibly slower access, storage suitable for utilization in long-term storage applications. Further, one or more of the decks may be configured to have more endurance than others of the decks. For instance, one or more of the decks may be suitable for a lifetime of approximately 100,000 cycles, whereas one or more others of the decks may be suitable for about 1,000,000 cycles (in other words, at least one of the decks may have a durability of at least about 10-fold more cycling times than another of the decks). The difference between the endurance of the decks may result from structural differences between the decks. For instance, a deck with higher endurance may have reduced thermal disturb and/or other memory-loss mechanisms as compared to a deck with less endurance. However, the deck with less endurance may have other advantages (for instance, faster access times, etc.) as compared to the deck with higher endurance. Accordingly, each memory array deck may be tailored for applicability relative to specific memory functions.

So now I am wondering about this machine learning from NVMdurance also being used on 3DXpoint and how far Intel would be able push the lower endurance fast access version of 3DXpoint in various categories?

Could Intel even reduce the latency further (while keeping acceptable endurance) via some reduction in retention time? (This particularly in the setting of using small 3DXpoint dies (stacked) with a higher number of channels* to keep keep write acceptable while boosting endurance**.)

Also would the FPGA 3DXpoint controller need to stay on the Optane DIMM or can it move to the CPU? (I am thinking it can probably move***)

*This, in contrast, to an Optane SSD where there are less channels and the dies are larger.

**The boost in endurance should come from the greater number of dies in parallel which means that each 3DXpoint doesn't need to be stressed as much in order to accomplish X level of write speed.

***This to a Xeon or EPYC CPU with FPGA attached.