nVidia scientist on Larrabee

[chizow]

Originally posted by: Idontcare
Not all possibilities carry the same probability of likelihood though, some are far-fetched (non-zero probability of occurring) but nonetheless are possible. I do have concerns for the folks who have already decided (with zero data for justification) that all scenarios but their preferred outcome have zero-probability of occurring...

Well again, you can look at it both ways I suppose (based on your expectations and hopes for Larrabee). I think you can see pretty clearly through the evolution of this thread there's a few individuals making unsubstantiated and largely inaccurate claims about Larrabee, followed by links to data points, reviews, industry speculation from people who are directly knowledgeable on the topic refuting or questioning those claims. And no I'm not including myself in that category, however, my conclusions are based on those references and data points.

 

[BenSkywalker]

My interpretation of this dialogue between you and vueltasdando is that you are discussing how the world should work in theory whereas vueltasdando is discussing how the world works in practice.

To that I would say let us wait and see how the current pending IP claims against Intel turn out. It is shocking how broad based some of the patents in the graphics industry are, it is akin to IBM's initial BIOS patents(which the court eventually had to throw out as there wasn't a viable workaround to it using the technology of the era).

I find this repeated talk of your implied checking account size to be distasteful.

When did I ever say any such thing? I guess you could say it was bad timing, but I stopped working with technology years before salaries exploded for the industry, while I enjoyed working with 3D, it still isn't a high paying profession by any means. I'm not even close to making seven digit salary, not remotely in the league of it. I bring up that I make a lot more money at what I do now mainly as a reference that I do a good job, nothing at all to do with my financial situation.

In my experience its the guys who feel they have to resort to talking about the size of their paycheck as a means to establish credibility that tend to be the one's that don't have much else worth listening to.

Do you know what the difference between relative and absolute is? I never made any particular claims to how much money I make, you assumed as much simply because I stated I make a lot more now then I used to. I live down the street from MIT, and no I am not a MIT grad, the competition for any job in the technology field in my area could only really be compared to living in the Valley, and we don't have close to as many lucrative jobs out here as they do out there. Given that the poster was inquiring about if I worked with technology or not, I was making clear why I didn't. It was easier for me to improve my standard of living by leaving the industry and going in a different direction. Said a different way, I made crap working in the industry, now I make a decent wage- not stellar, just decent

 

[Idontcare]

Originally posted by: BenSkywalker

My interpretation of this dialogue between you and vueltasdando is that you are discussing how the world should work in theory whereas vueltasdando is discussing how the world works in practice.

To that I would say let us wait and see how the current pending IP claims against Intel turn out. It is shocking how broad based some of the patents in the graphics industry are, it is akin to IBM's initial BIOS patents(which the court eventually had to throw out as there wasn't a viable workaround to it using the technology of the era).

I find this repeated talk of your implied checking account size to be distasteful.

When did I ever say any such thing? I guess you could say it was bad timing, but I stopped working with technology years before salaries exploded for the industry, while I enjoyed working with 3D, it still isn't a high paying profession by any means. I'm not even close to making seven digit salary, not remotely in the league of it. I bring up that I make a lot more money at what I do now mainly as a reference that I do a good job, nothing at all to do with my financial situation.

In my experience its the guys who feel they have to resort to talking about the size of their paycheck as a means to establish credibility that tend to be the one's that don't have much else worth listening to.

Do you know what the difference between relative and absolute is? I never made any particular claims to how much money I make, you assumed as much simply because I stated I make a lot more now then I used to. I live down the street from MIT, and no I am not a MIT grad, the competition for any job in the technology field in my area could only really be compared to living in the Valley, and we don't have close to as many lucrative jobs out here as they do out there. Given that the poster was inquiring about if I worked with technology or not, I was making clear why I didn't. It was easier for me to improve my standard of living by leaving the industry and going in a different direction. Said a different way, I made crap working in the industry, now I make a decent wage- not stellar, just decent

Yeah I was just reading way to much into the "lots of bonus checks" comment above then, my bad, I read far more into it than was merited or intended. Thanks for being cordial about it in your reply, not that I expected any less of you, but you'd have been well within your rights to drop a choice word or two at me regarding getting off my high horse As always, thanks for taking the time to clarify your position on the topic at hand.

 

[IntelUser2000]

Originally posted by: chizow

I'm not sure what you are getting at, perhaps the same thing, but my point was that cache makes up a significant portion of traditional CPUs, the simplest transistor, allowing clock speeds to scale higher. Those die shots are consistent with my point, showing 40-50% of that die space being dedicated to cache.

That's very different than GPUs which are dedicating at least that much of their die space to execution units rather than cache. Translated to Larrabee, where each discrete core will be a mix of both cache and functional/execution units sets the expectation of clockspeeds being closer to those of a GPU, rather than Intel's CPUs, especially given the estimated size and TDP of Larrabee.

There's no difference. It's very complex+simple(core vs caches in CPU) vs relatively complex(GPU). GPUs have shaders, which aren't really cores

Look at the GT200 die shot: http://www.anandtech.com/video/showdoc.aspx?i=3334

Even with the die micrograph you can clearly see it has significant amount of repetitive circuits put together.

In Nehalem, only 50mm2 out of the 263mm2 die is L2 and L3 caches. In Beckton, out of the ~600mm2 or so die size, the 8x 256KB L2 and 24MB L3 will occupy only 160mm2.

When there's so many damn repetitive units like in GPUs, it can be optimized for space. While its more than complex than cache, its nowhere near complex as non-cache CPU. In the end its all same.

And yes I agree that Intel has more experience with larger chips.



Oh, and about the "x86 tax". Let me briefly state what the engineer from AMD said about decoder size in their Athlon processors. "Each of the 9 decoders in the Athlon processors only take about the space of 4KB SRAM". I don't know why they stated 9 decoders when there's only 3, but the total space taken up by the decoders are equal to mere 36KB.

With Intel's 45nm process, SRAM takes only 6mm2 per MB of capacity. Since AMD's SRAM is less dense let's assume in Intel terms that the "9 decoders" as stated by the AMD engineer takes space equal to 72KB of SRAM. In Larrabbee, it only has 2 decoders, which is less than the 3 in Athlon CPUs, so lets take that 72KB figure and cut it by 1/3, making it approximately 50KB.

Let's assume that Larrabbee will have 48 cores for the 600mm2 die version. 50KB x 48 is approximately 2.4MB, which even with conservative estimates it'll only take up 15mm2. Inefficient circuitry placement itself will cost most than 15mm2!!

Sure you can call 2.5% usage of space tax if you so wish. But that's nothing that can't be overcome by clever design.

Back in 1996 when the first Pentium was running at 0.35u or even 0.5u, it was a significant impairment. Its no longer true now.

 

[Keysplayr]

Originally posted by: IntelUser2000

Originally posted by: chizow

I'm not sure what you are getting at, perhaps the same thing, but my point was that cache makes up a significant portion of traditional CPUs, the simplest transistor, allowing clock speeds to scale higher. Those die shots are consistent with my point, showing 40-50% of that die space being dedicated to cache.

That's very different than GPUs which are dedicating at least that much of their die space to execution units rather than cache. Translated to Larrabee, where each discrete core will be a mix of both cache and functional/execution units sets the expectation of clockspeeds being closer to those of a GPU, rather than Intel's CPUs, especially given the estimated size and TDP of Larrabee.

There's no difference. It's very complex+simple(core vs caches in CPU) vs relatively complex(GPU). GPUs have shaders, which aren't really cores

Look at the GT200 die shot: http://www.anandtech.com/video/showdoc.aspx?i=3334

Even with the die micrograph you can clearly see it has significant amount of repetitive circuits put together.

In Nehalem, only 50mm2 out of the 263mm2 die is L2 and L3 caches. In Beckton, out of the ~600mm2 or so die size, the 8x 256KB L2 and 24MB L3 will occupy only 160mm2.

When there's so many damn repetitive units like in GPUs, it can be optimized for space. While its more than complex than cache, its nowhere near complex as non-cache CPU. In the end its all same.

And yes I agree that Intel has more experience with larger chips.



Oh, and about the "x86 tax". Let me briefly state what the engineer from AMD said about decoder size in their Athlon processors. "Each of the 9 decoders in the Athlon processors only take about the space of 4KB SRAM". I don't know why they stated 9 decoders when there's only 3, but the total space taken up by the decoders are equal to mere 36KB.

With Intel's 45nm process, SRAM takes only 6mm2 per MB of capacity. Since AMD's SRAM is less dense let's assume in Intel terms that the "9 decoders" as stated by the AMD engineer takes space equal to 72KB of SRAM. In Larrabbee, it only has 2 decoders, which is less than the 3 in Athlon CPUs, so lets take that 72KB figure and cut it by 1/3, making it approximately 50KB.

Let's assume that Larrabbee will have 48 cores for the 600mm2 die version. 50KB x 48 is approximately 2.4MB, which even with conservative estimates it'll only take up 15mm2. Inefficient circuitry placement itself will cost most than 15mm2!!

Sure you can call 2.5% usage of space tax if you so wish. But that's nothing that can't be overcome by clever design.

Back in 1996 when the first Pentium was running at 0.35u or even 0.5u, it was a significant impairment. Its no longer true now.

Are you certain that the term "tax" was directed at die space utilized, or a performance tax for an X86 CPU doing GPU specific tasks?

?Intel?s chip is lugging along this x86 instruction set, and there is a tax you have to pay for that,? Mr. Dally said.

"Intel says that staying with x86 makes life easier on software developers familiar with such an architecture. Mr. Dally rejects this by saying Intel will need to take up valuable real estate on the chip to cater to the x86 instructions."

I have a feeling that it's going to take a bit more space than 15mm2. After all, every Core in Larrabee is an X86 CPU.

 

[IntelUser2000]

Originally posted by: Keysplayr

Are you certain that the term "tax" was directed at die space utilized, or a performance tax for an X86 CPU doing GPU specific tasks?

Yes it was. I don't know the exact quote but it was in the line of what I said:
"Each of the 9 decoders takes space approximately equal to 4KB of SRAM"

 

[Keysplayr]

Originally posted by: IntelUser2000

Originally posted by: Keysplayr

Are you certain that the term "tax" was directed at die space utilized, or a performance tax for an X86 CPU doing GPU specific tasks?

Yes it was. I don't know the exact quote but it was in the line of what I said:
"Each of the 9 decoders takes space approximately equal to 4KB of SRAM"

See above for quote.

So, is that all an x86 CPU is? Decoders? By that logic, a Penryn CPU should only be slightly larger than the head of a pin, Plus cache. I'm not following you here. decoders may take up such little space, but what about the rest of the CPU the decoders need to function with?

 

[IntelUser2000]

Oh ok a bit of misunderstanding there, I apologize.

The term "x86 tax" here means how much extra die it will take to support the x86 instruction set. Ever since the original Pentium the x86 CPUs used decoders to decode x86 instructions into simpler "RISC" instructions for the CPU to process(because the x86 instruction set was archaic or whatever). So the "tax" is exactly how much it'll take to put the decoders which wouldn't have been needed on an non-x86 architecture.

Larrabbee uses the x86 instruction set, Nvidia/ATI GPUs don't, hence the "tax" on Larrabbee. Now that's not a problem on complex cores like Nehalem, but as the cores become simpler like Larrabbee to support more cores, the tax becomes greater.

 

[Keysplayr]

Ok, thanks. But now this gets me thinking about what dally meant. If Larrabee will have a die size of over 600mm2, Why would Dally feel that 15mm2 dedicated to x86 instructions is a high tax to pay when the die would still be an enormous 585mm2 without it? This is why I think he meant something other than just die space.

 

[myocardia]

Originally posted by: BenSkywalker
Everyone seems to be taking the stance that Larrabee must have a lot going for it because of how much Intel is putting into it. Intel i740 anyone?

Corrected that for you.

 

[IntelUser2000]

Originally posted by: Keysplayr
Ok, thanks. But now this gets me thinking about what dally meant. If Larrabee will have a die size of over 600mm2, Why would Dally feel that 15mm2 dedicated to x86 instructions is a high tax to pay when the die would still be an enormous 585mm2 without it? This is why I think he meant something other than just die space.

Ehh, it looks like it'll take something in the range of 30-40mm2. Well anyway that's not ground-breaking.

Back in the Pentium days when we were running with 0.5um processors, the decoders took enough die space to possibly hamper the performance. Nowadays we are running on 45nm which makes it more than 100x smaller.

While myself doubt it would be a top performer in 3D, the amount of resources Intel is pouring into the project makes me think it'll at least be a significant competitor.

Let me tell you guys this. As long as the project isn't delayed, it'll be at least worth something to live up to the die size. Delays are what kills projects like these.

 

[Idontcare]

Originally posted by: IntelUser2000

Originally posted by: Keysplayr
Ok, thanks. But now this gets me thinking about what dally meant. If Larrabee will have a die size of over 600mm2, Why would Dally feel that 15mm2 dedicated to x86 instructions is a high tax to pay when the die would still be an enormous 585mm2 without it? This is why I think he meant something other than just die space.

Ehh, it looks like it'll take something in the range of 30-40mm2. Well anyway that's not ground-breaking.

Back in the Pentium days when we were running with 0.5um processors, the decoders took enough die space to possibly hamper the performance. Nowadays we are running on 45nm which makes it more than 100x smaller.

While myself doubt it would be a top performer in 3D, the amount of resources Intel is pouring into the project makes me think it'll at least be a significant competitor.

Let me tell you guys this. As long as the project isn't delayed, it'll be at least worth something to live up to the die size. Delays are what kills projects like these.

It is hard to read much into what motivated Dally to make the comments he did, but given who enables him to pay his mortgage does it really take any stretch of the imagination to conclude the cons of Larrabee are going to be more overstated than understated by him?

I mean he wasn't hired by NV to go on a press gambit to talk-up the superiority of Larrabee, right?

As for the decoder space...I've scratched my head over the comments in this thread. 40% of the diespace in each core goes for the decoders?

Here is a die-map for a PentiumIII, this was a 3-wide ID for 0.25um Katmai (9.5m xtors, 10.4mm x 12.3mm die) surely the instruction decoders are on the same order of complexity as that of a pentium-based larrabee core (if not more so).

The die area for the 3-wide ID is approximately 9.2 mm^2 and 685k xtors on the 0.25um Pentium III.

Scaling to 45nm, we'd expect 685k xtors to roughly occupy around 0.23 mm^2...(based on 246mm^2 for 732m xtors on Nehalem).

So exactly along the lines of what IntelUser is saying, even for a 64-core Larrabee we'd expect maybe 16 mm^2 ( = 64*0.25mm^2) of the total die area to be dedicated to the 64 instruction decoders, and that is assuming they are as complicated as the P3's decoders were. A 3% die-area tax to maintain x86 hardware level compatibility seems like a pretty good bargain.

As others have said the question remains as to what level of performance-tax the x86 decoders impart...but history has foretold the unavoidable death of x86 for decades now for this same reason. Were I a betting man I would not bet against the house here.