Now if we could just assimilate this little beast...

[ColinP]

http://www.wired.com/news/technology/0,1282,37285,00.html




Col

 

[convex]

"Running a parallel version of IBM's AIX, Big Blue's flavor of UNIX, the ASCI White supercomputer takes two hours to boot up."

bah

"It requires the constant attention of a small army of systems administrators. Because of the sheer number of parts, it tends to break down, although IBM said the machine will run 100 hours without crashing."

bah again

 

[ColinP]

Only slightly longer to boot up than my NT4 laptop then...

 

[Simulacrum]

Previously, dnet had the fastest combined "computer" on the planet, with a speed of over 10 Teraflops/sec. Today's average speed was just 12.4 Teraflops/sec. ASCI White is going to do 12.3 Teraflops/sec. Dnet may not have the fastest computer for much longer, considering IBM plans on releasing a much faster version of ASCI white.

There's no denying that this is a very powerful computer.

 

[CurtOien]

Today SETI had 12.33 TeraFLOPs/sec

 

[amok]

Wow, I didn't realize that ASCI white can perform as many ops as the entire S@H or d.net projects! I didn't even think to pay attention to that little detail.

And yes, IBM is expecting to increase the speed of their next ASCI computer (its going to be some color other than white )by nearly a factor of 10! They're hoping to put together a 100TFLOPS computer by something like 2003.

On an interesting side note, doesn't IBM plan on being able to put something like 8 of their current cores onto a single die? If they were to make that happen and build an exact replica of ASCI white with the new 8 core processors they could hit 98.4TFLOPS! I think I see the picture coming together now for their new comp .

 

[BurntKooshie]

amok - are you thinking of the Power4? That's two CPU's on one die, and they both share a common L2 cache (on die as well, and Sledge hammer will be the same idea. 100gb/sec bandwidth ). These indivudual dies will be grouped into fours, which themselves can be grouped together. They all have L3 cache. a 333mhz (10gb/sec) bus to the L3 bus, and a 500mhz (10gb/sec) bus (wavepipelined....i sortaunderstand what that means) to each 4 die module....basically, a freaking BEAST.

For more info (this is where i got mine ) go to http://www.chips.ibm.com/news/1999/microprocessor99.pdf. Hehe...and to think, this ISN'T the CPU forum! (no Hyper99 to bother me! Wooooooooh! )