- Oct 14, 1999
- 11,999
- 307
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Northbridge chipsets, specifically their DRAM memory controllers, seem to have memory buffers in order to smooth out performance issues running asynchronous speeds between the memory and the front-side bus. I've got some real quick questions about these buffers.
1. Are the buffers any signifigant size? If so, how big are they?
2. Would hammer's integrated controller require a buffer?
3. Do the buffers retain information until the next address is requested, thereby speeding up the recall if the memory address is the same as the last request?
4. Do these buffers run at fsb speed, at the memory speed, or are they running at the highest speed between the two interfaces?
5. What limits the design of these buffers?
Thanks in advance.
1. Are the buffers any signifigant size? If so, how big are they?
2. Would hammer's integrated controller require a buffer?
3. Do the buffers retain information until the next address is requested, thereby speeding up the recall if the memory address is the same as the last request?
4. Do these buffers run at fsb speed, at the memory speed, or are they running at the highest speed between the two interfaces?
5. What limits the design of these buffers?
Thanks in advance.
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