Next gen Zen 2/3 "Starship" and derivatives

[Spartak]

OK, this post is about the next generation of Zen on 7nm. A few questions to get this thread going:

1. Is there a Zen+ in between Zen (1st gen 14nm) and Zen2 (1st gen 7nm)? and if so, will this include IPC improvements?

2. With Starship rumoured to be 48 cores, is Starship another name for Rome?

3. Will Starship feature six dual quadcore CCX dies, or four dual hexacore CCX dies? If the latter (CCX increase from 4 to 6 cores), what does this mean for the next gen Zen CPU's and APU's. Is there any chance we will see 6core Gray Hawk APU's and up to 12 core next gen Pinnacle Ridge successors?

 

[swilli89]

We probably won't have anything substantial to discuss given AMD hasn't even finished rolling out Zen-based cores. Naples has just started to hit the market and Raven Ridge is still probably a full quarter or more away from release. Given that 7nm products probably won't be hitting shelves until 1H 2019 I'd say we see a "Zen+" sometime next year with a possible slight clockspeed bump based on new spins of the silicon. Doubtful there will be any meaningful IPC increases but that is 100% my assumption. Zen needs frequency increases for now, its IPC is already excellent.

I believe "Rome" is the "zen" equivalent as in it is the actual CCX to be scaled out and "Starship" is analogous to "Naples".

Lastly yes, Rome will be 6-core CCX by most accounts.

 

[Spartak]

Yes I know there is very little info to go on but since some people here are way more informed than me, I thought it would be nice to have a thread where info on the next generation of Zen could be shared and discussed.

Concerning the codenames, it used to be Naples>Rome>Milan, but then all of a sudden we saw Starship mentioned instead of Rome. Which I think is rather odd.

What I also find remarkable is if Rome / Starship is a 6-core CCX part, why does Gray Hawk still stay a 4CCX part, when both will be Zen2 on 7nm?

Maybe gray hawk will be exclusively for mobile focussing on low power, and the desktop APU's and CPU's will move to a separate 6core CCX design?

 

[Schmide]

Lastly yes, Rome will be 6-core CCX by most accounts.

Most accounts? I disagree. Other than pure speculation, this is absolutely not the case.

 

[swilli89]

Most accounts? I disagree. Other than pure speculation, this is absolutely not the case.

So Starship is somehow going to have 6 8-core dies on a single package? Have you seen how massive a package Naples already is? No.. only way to get 48 cores into a single package is with 6-core CCX's.

 

[Spartak]

So Starship is somehow going to have 6 8-core dies on a single package? Have you seen how massive a package Naples already is? No.. only way to get 48 cores into a single package is with 6-core CCX's.

Starship is 7nm, so a double 4CCX chip will be significantly smaller than on 14nm (a classic die shrink). So it will be about the same total area, but 6 smaller dies.

I'm thinking Milan (Zen3) might be where they shift from 6x 2*4CCX to 4x 2*6CCX, alongside 6CCX+GPU Desktop APU's and 2*6CCX Desktop CPU's.

A 2*6CCX core will give them much more flexibility with core counts, ranging from 12/10/8 all the way down to 6. But for Zen2 it might be too ambitious.

 

[noneis]

Starship is 7nm, so a double 4CCX chip will be significantly smaller than on 14nm (a classic die shrink). So it will be about the same total area, but 6 smaller dies.

I'm thinking Milan (Zen3) might be where they shift from 6x 2*4CCX to 4x 2*6CCX, alongside 6CCX+GPU Desktop APU's and 2*6CCX Desktop CPU's.

A 2*6CCX core will give them much more flexibility with core counts, ranging from 12/10/8 all the way down to 6. But for Zen2 it might be too ambitious.

I doubt Zen 2 die has 8 Cores. I don't think that would retain compatibility with 2P Epyc boards. There are links between corresponding dies on 2P boards - 4 Links. Unless there are 6 links on those boards and AMD managed to hide it, Zen 2 die will most likely have 12 cores.

 

[Spartak]

I doubt Zen 2 die has 8 Cores. I don't think that would retain compatibility with 2S Epyc boards. There are links between corresponding dies on 2S boards - 4 Links. Unless there are 6 links on those boards and AMD managed to hide it, Zen 2 die will most likely have 12 cores.

Who's talking eight cores? The question is 4*CCX or 6*CCX. With "Zen2 most likely having 12 cores" I think you mean a double 6*CCX? That's doubtful when Gray Hawk is confirmed to be up to 4/8 C/T; which'd mean mobile/APU remains on a smaller 4*CCX, which I find unlikely.

 

[noneis]

Who's talking eight cores? The question is 4*CCX or 6*CCX. With "Zen2 most likely having 12 cores" I think you mean a double 6*CCX? That's doubtful when Gray Hawk is confirmed to be up to 4/8 C/T; which'd mean mobile/APU remains on a smaller 4*CCX, which I find unlikely.

Starship is 7nm, so a double 4CCX chip will be significantly smaller than on 14nm (a classic die shrink). So it will be about the same total area, but 6 smaller dies.

48/6 = 8.

If APU Grey Hawk has four Zen 2 cores then, full Zen 2 die is most likely 3 CCXs (3*4).

 

[Schmide]

So Starship is somehow going to have 6 8-core dies on a single package? Have you seen how massive a package Naples already is? No.. only way to get 48 cores into a single package is with 6-core CCX's.

The only way??? I would believe AMD would be much more likely to just add another CCX to its die than to totally redesign their basic building block.

3 x 4 core = 12 x 4 = 48

Edit: Seriously think about this for a second.

AMD has basically had 3 designs over the past 20 years.

G-series -> Cat cores (Bobcat, Jaguar, etc)

K6-K7-K8-K10 (Thunderbird, Hammer, Phenom, II)

Bulldozer (Piledriver, Steamroller, Excavator)

They don't change things as much as they tweak things.

 

[William Gaatjes]

The only way??? I would believe AMD would be much more likely to just add another CCX to its die than to totally redesign their basic building block.

3 x 4 core = 12 x 4 = 48

I agree.
AMD has a thing for a multiple of 4cores.
It makes sense to add another 4 core CCX while improving the existing CCX where possible and improving communications between the several CCX.

 

[formulav8]

When it comes to Zen+, I kinda see a BD to PD style increase. 0-7% IPC and some higher potential clocks. I doubt they could do much more with 14nm+.

 

[Tuna-Fish]

It's important to note that cores are not the only thing found in dies. AMD is committed to having their next server CPU be socket-compatible with current EPYCs. This means 8 memory channels and 128 PCI-E, which means there has to be a power-of-two amount of chips under the heatspreader. I'd bet on them going with the 4. This, and 48 cores, means that either they use a 6-core CCX, or put 3 CCX in a single die. Of these, I'd bet on the 6-core CCX.

 

[Etheoma]

Starship is 7nm, so a double 4CCX chip will be significantly smaller than on 14nm (a classic die shrink). So it will be about the same total area, but 6 smaller dies.

I'm thinking Milan (Zen3) might be where they shift from 6x 2*4CCX to 4x 2*6CCX, alongside 6CCX+GPU Desktop APU's and 2*6CCX Desktop CPU's.

A 2*6CCX core will give them much more flexibility with core counts, ranging from 12/10/8 all the way down to 6. But for Zen2 it might be too ambitious.

I thought somewhat simmlarly but really think about it, and look at how Naples communicates with the RAM with 4 DIMMS per die it simply wouldn't work with 6 dies which would mean a platform change, also it would mean more pins which is the main reason for the size of the TR4, which would mean creating a new socket just for Zen 2 and that is a real no no for servers as your server owners are much more likely to update there CPU's than consumers so it would make no sense at all for them to give consumers compatibility between Ryzen and Zen 2 and not servers, and it is a much bigger pain in the ass for data centers to have to change all there motherboard etc.

No either the 48 core is not happening or it is a 12 core die.

Edit; to add a cherry ontop of why they wouldn't you would be able to have 192 PCIe lanes on a 6 x 8 core Epyc CPU but without a platform change you wouldn't be able to use them and really you would have a massive back lash from data centres if you didn't give them access to the new CPU's without completely disassembling there hole data centre...

Edit 2; also it just make a lot of sense as I don't think AMD is going to be able to completely catch up on IPC and clockspeeds there going to be close but not completely caught up, so they need to keep there core advantage or at least not completely lose it, and with Icelake Intel is moving to 8 cores 16 threads so If AMD doesn't move to 12 cores they are going to lose there advantage completely.

But I don't think you are getting a 12 core CPU for $300 - 350 they are going to start them at $400+ and $500 for the high end model, the reason I think AMD made the 1800X was for this propose, because no one is really buying it... I think they just wanted to have a product in there main stream platform so they could say when Zen 2 comes, "look we have increased the core count by 50% and it's the same price!!!" /

But in reality no one was buying the 1800X to begin with so it's a price increase, but if they can increase IPC by 5 - 7% and get a 15% uplock that should be able to beat out a 16 core Intel Skylake X CPU and come pretty close to the 18 core and considering Intel wont have launched there "Cannonlake X" parts yet AMD with that can do the same thing the did with Ryzen but this time they will be able to crush Intel on there Perf/Watt, annihilate them on the Price / Performance And crush there old 16 core at the same time but not to the same degree in those categories.

So no one will really be complaining about a defacto price increase when the 10 core is still a big jump over the 1700 / 1700X and the $425~ and $500 price points will actually be worth there price delta if you are doing content creation or HEAVY multi tasking.

So AMD gets the PR win of having 25% more cores than Intel and is close enough to Intel's single threaded performance that it doesn't really matter all that much so you might as well go with the CPU with 2 more cores or go for the 8 core 16 thread which will be about the same price as Intel's i5 so you can either save money and get nearly identical performance or "future proof" your self a little by buying the 10 core although AMD might decide the 8 core will interfere too much with there 10 core and lock it down to 8 cores 8 threads depending on how well AMD is fairing against Intel.

That is the beauty of launching latter you can respond in an exact way which will sink your competition, although they will need to announce and advertise the 12 core thing before Intel starts talking about the fact that they are going to 8 cores 16 threads to sink that then they can wait until after Intel's launch to see what they should do for there lower end parts.

So AMD really needs to start talking about this at the end of HL1 2018 which would kind of sink Pinnacle Ridge as well... although I think it's worth it because Pinnacle Ridge was always going to be a poor seller with Intel launching Icelake not long after and it's better for Pincale Ridge to get sunk by there own PR than by Intel's.

Although they may make the mistake of waiting too long which would be a real shame because if I am right Zen 2 is going to be pretty epic, no pun intended although if they can get Pinncale Ridge out of the door EARLY 2018 I mean February March would really be pushing it then they have 3 months to sell as many of those CPU's as they can before they crash the sales with there own PR.

 

[Arachnotronic]

So Starship is somehow going to have 6 8-core dies on a single package? Have you seen how massive a package Naples already is? No.. only way to get 48 cores into a single package is with 6-core CCX's.

I think you are missing something that AMD can do in your analysis.

 

[raghu78]

I think you are missing something that AMD can do in your analysis.

3 CCX x 4 cores per CCX or 2 CCX x 6 cores per CCX are the 2 options for AMD. Of these options the easier option might be 3 x 4 cores per CCX. AMD might wait till Zen 3 to change the CCX layout. For Zen 3 I think AMD might go for 8 core CCX and 16 core Ryzen die. I think AMD will increase fabric speeds on Zen 2 at 7nm to reduce CCX latency and memory latency.

 

[Etheoma]

3 CCX x 4 cores per CCX or 2 CCX x 6 cores per CCX are the 2 options for AMD. Of these options the easier option might be 3 x 4 cores per CCX. AMD might wait till Zen 3 to change the CCX layout. For Zen 3 I think AMD might go for 8 core CCX and 16 core Ryzen die. I think AMD will increase fabric speeds on Zen 2 at 7nm to reduce CCX latency and memory latency.

I think going to 6 cores per CCX would offer better performance though and given the work they are already having to put into die shinking ya might as well change the CCX layout while your at it, although the performance delta would only be like 1 - 2% but when I am only looking for a 5 - 7% IPC increase 1 - 2% has you a significant amount of the way there, the main thing though at an arctectural level that is holding them back is the infinity fabric latency if they could reduce that by halve then that also decreases you RAM latency by 40% which is one of Ryzen's big flaws, although decreasing the fabric latency by 50% is no easy task... Although they may never address it because DDR5 with a presumed double frequency over DDR4 would increase the fabric clock and decrease fabric latency.

Seriously though it will be freaking amazing if AMD can do a 95W 12 core part, although that 95W's is kind of BS and is based on the base clock rather than the all core boost, it's more like 120W but still as 12 core within a 120W TDP is still pretty freaking good, but even if they can't they still have more gas in the AM4 engine as it can support upto 140W parts but even that will be pretty amazing.

 

[el etro]

Zen+ is likely a respin for already existent Zen lineup. Performance uplift thanks to the density/performance benefits the 14nm+ (named 12LP by GloFo PR) gives.

 

[lixlax]

Now that CF is here and Intels 6C matches Zen 8-core in MT tasks its clear that Pinnacle ridge has to deliver in clocks and max OC for AMD to stay competitive. Intel is currently OC'ing about 25% higher which is a huge amount. A healthy 10-15% higher clocks would bring Ryzen much closer to Intel's ST and make it clearly faster than CF 6-core in MT.

 

[Etheoma]

Zen+ is likely a respin for already existent Zen lineup. Performance uplift thanks to the density/performance benefits the 14nm+ (named 12LP by GloFo PR) gives.

If you were talking to me about the 12LP die shink if you are getting a density increase you can fairly say that they have shrunk the node because everything is PR because fin pitch doesn't really change anymore so all you can measure is the density, to compare it to Intel's 14nm + and 14++ is unfair as those did not increase density a respin is simply refining the way you make a node not actually increasing the density, Although Intel's 14nm node in density terms is comparable to GF's 12nm node but still.

For example you could call everything Intel, GF, TSMC etc have done after 32nm a respin of that node but that would be dumb because density has increased even though fin pitch has not changed due to FinFETs which make such a measurement useless

But I already knew it would only be an upclock I was talking about Zen 2 where AMD has promised a IPC uplift, I think you are getting Zen 2 on "7LP" mixed up with the simple die shrunk Zen 1 which will simply be a clockrate increase, hopefully by 10%.

Also Zen 3 is only going to be a refined "7LP" made on EUV rather than DUV so I think that is where AMD will focus on IPC and we might see a 10% ish IPC up lift as I doubt they are going to head for 16 cores and clockspeed will likely not be able to be increased significantly and changing from DUV to EUV should not mean much re-engineering simply to transfer it, so first it's there only option for increased performance for the most part and second they will not be too busy with other stuff to do it.

While Zen 2 they have to translate Zen to 7nm, push higher clocks, hopefully tackle the infinity fabric latency and get a small IPC increase, they don't have the time for a big IPC increase. Although Intel is likely looking towards a group up design for 2022 which will offer big IPC uplifts so I only see AMD holding all the cards for maybe a year then Intel will have everything over AMD again, but hopefully beyond Zen 3 they have something big planned so that Intel can only hold the lead for a year.

 

[Vattila]

Hi all, here's what I expect for Ryzen, Threadripper and EPYC CPUs throughout the current public AMD roadmap, spanning 2018-2020:

The "Zeppelin" die based on the "Zen" core and manufactured on the 14LPP process will be followed by 12LP "Zeppelin+" this year for the Ryzen and Threadripper 2000 series. Frequency and IPC will increase slightly. Core count stays the same at up to 8 cores for Ryzen and 16 cores for Threadripper. EPYC remains at 14LPP with up to 32 cores.

The 7LP "Starship 1" die based on the "Zen 2" core follows in 2019, with 3 quad-core CCXs per die, enabling the Ryzen and Threadripper 3000 series with up to 12 and 24 cores, respectively. EPYC 2 ("Rome") will get up to 48 cores. Frequency and IPC for "Starship 1" will increase noticeably.

Then the 7LP+ "Starship 2" die based on the "Zen 3" core follows in 2020, with 4 quad-core CCXs per die, enabling the Ryzen and Threadripper 4000 series with up to 16 and 32 cores, respectively. EPYC 3 ("Milan") will get up to 64 cores. Frequency and IPC for "Starship 2" will increase slightly.

That's a straight-forward roadmap for the CPUs. But what will happen for the APUs?

 

[CatMerc]

Hi all, here's what I expect for Ryzen, Threadripper and EPYC CPUs throughout the current public AMD roadmap, spanning 2018-2020:

The "Zeppelin" die based on the "Zen" core and manufactured on the 14LPP process will be followed by 12LP "Zeppelin+" this year for the Ryzen and Threadripper 2000 series. Frequency and IPC will increase slightly. Core count stays the same at up to 8 cores for Ryzen and 16 cores for Threadripper. EPYC remains at 14LPP with up to 32 cores.

The 7LP "Starship 1" die based on the "Zen 2" core follows in 2019, with 3 quad-core CCXs per die, enabling the Ryzen and Threadripper 3000 series with up to 12 and 24 cores, respectively. EPYC 2 ("Rome") will get up to 48 cores. Frequency and IPC for "Starship 1" will increase noticeably.

Then the 7LP+ "Starship 2" die based on the "Zen 3" core follows in 2020, with 4 quad-core CCXs per die, enabling the Ryzen and Threadripper 4000 series with up to 16 and 32 cores, respectively. EPYC 3 ("Milan") will get up to 64 cores. Frequency and IPC for "Starship 2" will increase slightly.

That's a straight-forward roadmap for the CPUs. But what will happen for the APUs?

I agree with everything aside from the Zen 3 frequency and IPC. Well, frequency I expect to increase slightly, but a big enough change in the core architecture to call it Zen 3 is likely nothing small.

Also I have a suspicion. The two dies are in development together, and that happened due to AMD closer to Zen's release realizing their core ended up being more competitive than expected due to Intel faltering, and they want to capitalize on that. Therefore they started developing a 16 core die to go along the 12 core die. Yes the development costs would be large, but the return for having literally double the cores of Intel would be too good an opportunity to waste.

Zen 3 I think will again have only die, this time 16 cores per die like last time, and only have IPC and some freq uplifts.

 

[ksec]

Hi all, here's what I expect for Ryzen, Threadripper and EPYC CPUs throughout the current public AMD roadmap, spanning 2018-2020:

The "Zeppelin" die based on the "Zen" core and manufactured on the 14LPP process will be followed by 12LP "Zeppelin+" this year for the Ryzen and Threadripper 2000 series. Frequency and IPC will increase slightly. Core count stays the same at up to 8 cores for Ryzen and 16 cores for Threadripper. EPYC remains at 14LPP with up to 32 cores.

The 7LP "Starship 1" die based on the "Zen 2" core follows in 2019, with 3 quad-core CCXs per die, enabling the Ryzen and Threadripper 3000 series with up to 12 and 24 cores, respectively. EPYC 2 ("Rome") will get up to 48 cores. Frequency and IPC for "Starship 1" will increase noticeably.

Then the 7LP+ "Starship 2" die based on the "Zen 3" core follows in 2020, with 4 quad-core CCXs per die, enabling the Ryzen and Threadripper 4000 series with up to 16 and 32 cores, respectively. EPYC 3 ("Milan") will get up to 64 cores. Frequency and IPC for "Starship 2" will increase slightly.

That's a straight-forward roadmap for the CPUs. But what will happen for the APUs?

As CatMerc said, either there is no IPC improvement in Zen+, or Zen 3 actually have some decent IPC improvement. Kind of hard to think both Zen+ and Zen 3 offer slight IPC improvement.

Just to add on the time line, Zen 2 will likely be out in early 2019, and Zen 3 is late 2020, So while it may only seem like a year apart, it is actually closer to 2 year.

On APU, I am hoping to see 8 Core APU in 2020?

 

[scannall]

As CatMerc said, either there is no IPC improvement in Zen+, or Zen 3 actually have some decent IPC improvement. Kind of hard to think both Zen+ and Zen 3 offer slight IPC improvement.

Just to add on the time line, Zen 2 will likely be out in early 2019, and Zen 3 is late 2020, So while it may only seem like a year apart, it is actually closer to 2 year.

On APU, I am hoping to see 8 Core APU in 2020?

Not too sure about that. 2020 should see DDR5, and PCIe 4/5. That's plenty to work on for now. Plus clearing up low hanging fruit.

 

[french toast]

Zen 2 should have a decent IPC jump, also 6 core ccx for 12 core "peak ridge" die.(or whatever it's called).
This would allow raven ridge successor to equal intel with one ccx = 6/12.

I think clocks will be a bit better than 12nm, might match intel coffeelake.