New Zen microarchitecture details

[krumme]

Why did Jim Keller already leave in 2015? Was he finished and happy, or was it something else behind the curtains?

Surely he have laid the foundation of what comes the next 3 years at least. I think he was well into the zen tock 1 2 and 3. And then just building the organization and team for it.
Apple a4 and a5 looked like small steps but i am sure what happened after that with a6 and a7 was also a result of his strategic work.
I think he have shown enough merrits to mark he is absolutely one of the best.
He has never been a place many years.
Surely he and Papermaster probably disagree about a lot of stuff like eg the priority of k12 but i dont think him leaving is a result of that. He probably got all implemented. It surely looks like a lot happened.

 

[Tuna-Fish]

Why did Jim Keller already leave in 2015? Was he finished and happy, or was it something else behind the curtains?

The way I understood it, Keller wanted to push the K12 ARM server core, and AMD canned (or at least delayed) it in order to concentrate on shipping Zen. This irked Keller.

 

[krumme]

I hope the guy responsible for Bulldozer isn't still in an important position.

Its wrong to say a single person like Dirk Meyers is solely responsible for bd. As well as eg saying keller is solely responsible for zen. Its not that simple. Even if we like to look for heroes and villains to reduce complexity its not the right way to look at it.
Meyers was eg also head of the team that made k7. Hardly a bad effort.
May i eg remind people that at this time up till launch of k7 no board makers would say they made a board and it was difficult to find a board. As i remember my asus k7 mb didnt even have the asus name printed on. K7 was a bang far beyond what zen is. In 1999 amd was nothing regarding tech and ip. So when amd entered with a big fat fpu that killed a p3 it was a shock.
But yeaa Dirk Meyers is now a advisor as i can tell so no harm done you can say

 

[Doom2pro]

I hope the guy responsible for Bulldozer isn't still in an important position.

It was more than just one person at fault...

http://www.xbitlabs.com/news/cpu/display/20111013232215_Ex_AMD_Engineer_Explains_Bulldozer_Fiasco.html

 

[majord]

32 links is accurate, 8 required by Promontory = 24 usable GP links. Since Promontory has some PCIe pass-through, the number of usable links might be slightly higher depending on the config.
You can come to the same conclusion by looking the server platform, even if you don't have the documents available. Naples has up to 128 links and no IO extender. 128 / 4 = 32.

AM1 (FS1r2) supports ECC as long as the motherboards are built with ECC support.

So, promontory has an x8 link back to AM4? (I've been working off the assumption it was x4 3.0, Like LGA1151)

 

[The Stilt]

So, promontory has an x8 link back to AM4? (I've been working off the assumption it was x4 3.0, Like LGA1151)

The "pass-through" PCIe (x8 Gen.2) would already allocate the x4 Gen. 3 alone. On top of the PCIe, Promontory has E-SATA (x2 each), SATA and USB, which all require PCIe lanes for communication.

 

[Thunder 57]

Has AMD done the impossible? To be able to leapfrog Intel with Ryzen despite the fact that Intel has 10x the R&D and manpower? Or is yet another hypetrain that will crash at launch?

Lisa Su seems extremely confident.

http://finance.yahoo.com/news/amd-ceo-why-its-good-to-be-the-smaller-guy-195512478.html

Compared to other CEO's; she is coming off as a technical wizard.

Not the CEO's job to understand what the company they are in charge of does?

Any wonder most CEOs are f**king inept and companies manage to get by in spite of them rather than because of them.

If the CEO cannot sit in a meeting and have a decent grasp of the fundamental elements of the issues that the worker-bees are facing in doing something, then they've no business in that business. No amount of shiny suits, slick haircuts and power-point bullsh!t will change that.


Edit: I suppose, somewhat contradictory to what I've said above - AMD's designing of Zen has involved a clearout of "managers" and allowing a small experienced group of engineers a free hand in getting on with it without being burdened by the gantt chart mafia.

It's amazing what engineers can do when lead by engineers rather than some bozo with an MBA.

 

[realibrad]

and isn't their next lake in 2018? They wont have the time to react fast enough if Ryzen is really good.

Intel has the funds to come back in a few years of they find it profitable.

 

[iBoMbY]

32 links is accurate, 8 required by Promontory = 24 usable GP links. Since Promontory has some PCIe pass-through, the number of usable links might be slightly higher depending on the config.
You can come to the same conclusion by looking the server platform, even if you don't have the documents available. Naples has up to 128 links and no IO extender. 128 / 4 = 32.

So you really think the 4 PCIe 3.0 lanes, and some PCIe 2.0 lanes, plus other I/O, which x370 offers, are connected to 12 PCIe 3.0 lanes on the CPU?

AM1 (FS1r2) supports ECC as long as the motherboards are built with ECC support.

Right. I was confusing something. I was thinking about "AMD Family 15h Models 60h-6Fh Processors", which are supporting ECC on the FP4 package, but not on the FM2r2 package. For AM4 (which is the successor of FM2r2, and was named FM3 previously), and "AMD Family 15h Models 70h-7Fh Processors" aka Bristol Ridge, this isn't entirely clear yet, but I don't see AMD mentioning anywhere they are supporting it on the AM4 package.

 

[Abwx]

For AM4 (which is the successor of FM2r2, and was named FM3 previously), and "AMD Family 15h Models 70h-7Fh Processors" aka Bristol Ridge, this isn't entirely clear yet, but I don't see AMD mentioning anywhere they are supporting it on the AM4 package.

Surely that Ryzen indeed support ECC, as for Bristol Ridge/Stoney Ridge they should support it as well since they will be used in embedded systems as replacement for current such socs.

• 
  "Merlin Falcon" (2015, 28 nm, SoC)
• Up to 4 "Excavator" x86 cores [51]
• GPU microarchitecture: Graphics Core Next (GCN) (up to 8 CUs) with support for DirectX 12
• Dual channel 64-bit DDR4 or DDR3 memory with ECC

https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_unit_microprocessors

 

[superstition]

Its wrong to say a single person like Dirk Meyers is solely responsible for bd. As well as eg saying keller is solely responsible for zen. Its not that simple. Even if we like to look for heroes and villains to reduce complexity its not the right way to look at it.
Meyers was eg also head of the team that made k7. Hardly a bad effort.
May i eg remind people that at this time up till launch of k7 no board makers would say they made a board and it was difficult to find a board. As i remember my asus k7 mb didnt even have the asus name printed on. K7 was a bang far beyond what zen is. In 1999 amd was nothing regarding tech and ip. So when amd entered with a big fat fpu that killed a p3 it was a shock.
But yeaa Dirk Meyers is now a advisor as i can tell so no harm done you can say

People also keep forgetting that Bulldozer isn't a recent architecture just because it's still on the market, as if it's the fault of its designers that AMD didn't have the cash needed to improve it enough.

We can thank things like the OEM deals, GenuineIntel, the big cost of buying ATI, and the like — not just gripe that an architecture from 2011/2012 hasn't held up well against anything after Sandy. There's also the matter of process node improvement, something that was mainly an issue with GF. The Stilt said the improvement in leakage, as I recall, was around 45%.

Desert of Kharak is a good example of how even the old hated PD architecture can still perform fine if the code takes advantage of it and so is stock Blender vs. The Stilt's compiles. The shortcomings of the Bulldozer architecture vs. Sandy's are hardly in the same league as the amount of performance just left on the table if the code isn't optimized.

If AMD had had that 45% better leakage and such back in 2011 it may have been able to keep more of the server market, at least for a while.

 

[R0H1T]

The way I understood it, Keller wanted to push the K12 ARM server core, and AMD canned (or at least delayed) it in order to concentrate on shipping Zen. This irked Keller.

Probably for good reason too, they're already preoccupied with a lot of things & expanding that further to ARM server space would spread them alarmingly thin especially with the very few resources they have atm.

 

[Nothingness]

Who do you think made the decision to have an F4 stepping as opposed to calling it a day at F3? Jim Keller who left months ago or the remaining Zen design leads + exec board?

The CEO and exec board don't make that kind of decisions in such a big company.

 

[Atari2600]

The CEO and exec board don't make that kind of decisions in such a big company.

I'll bet they did. Over the past 3 months, AMD are essentially a one product company - they live or die on Zen.

 

[KTE]

If the rumored 4C Zen is priced vs 4C Intel products, that'll be clear cut confidence that AMD has a winner.

Thanks,

I also found this interesting and am feeling hopeful

That made me feel the opposite.

Price/Performance can be achieved by low prices, as AMD has always done with many subpar products.

As far as I know, the architectural work was done by that stage - and Zen was in the process of taping out prior to debugging for bringing it to market.

JK finds that side of it a bit boring, so moved on.

Lol. He did the initial arch, then that's it. You push a new project, and if you achieve no funding, you find an interesting job elsewhere. It's standard.

Lisa Su --- Background in process
Mark Papermaster --- Background in architecture
Between the two of them, they'll be able to ask the right questions.

Over at Intel, the board are entirely process guys or marketeers (except possibly Rob Crooke, although his architecture background appears pretty light). It'd help explain why their tocks are pretty weak at the minute... although I suppose you'd wonder how the ticks are going wrong.

Thats nothing like how it works in the real world (and the ticks reasoning).

Management and exec don't care and don't get involved in ANY of this. They focus on managing the guy below them, stakeholders and PR.

People also keep forgetting that Bulldozer isn't a recent architecture just because it's still on the market, as if it's the fault of its designers that AMD didn't have the cash needed to improve it enough.

We can thank things like the OEM deals, GenuineIntel, the big cost of buying ATI, and the like — not just gripe that an architecture from 2011/2012 hasn't held up well against anything after Sandy.

It didn't hold up to anything 2007, forget after. It was a major regression.

With that process, get Istanbul 8C and it would be trounced.

The CEO and exec board don't make that kind of decisions in such a big company.

Not even upper management chains, yep.

Sent from HTC 10
(Opinions are own)

 

[superstition]

It didn't hold up to anything 2007, forget after. It was a major regression.

Hyperbole, at least in the case of PD. There are too many recent game benchmarks that show PD close to Sandy.

 

[The Stilt]

So you really think the 4 PCIe 3.0 lanes, and some PCIe 2.0 lanes, plus other I/O, which x370 offers, are connected to 12 PCIe 3.0 lanes on the CPU?

No?
None of the Promontory variants offer any PCIe Gen. 3 links, just up to 8 Gen. 2 links (X370) for general purpose. And those 8 Gen. 2 link require x4 Gen. 3 links from the CPU side.
Because there is plenty of other stuff in the IO extender too, the number of links it requires must be greater than just x4 Gen. 3 (I expect x8). And when the CPU has 32 links in total, that leaves 24 for other purposes (PCI-E & M.2).
Since Promontory offers up to 8 Gen. 2 links, you essentially get half of the links allocated by it back.

- So x32 Gen. 3 links in the CPU
- x8 Gen. 3 links connected to Promontory
- x24 Gen. 3 links left for GPP
- Up to 8 Gen. 2 links usable through Promontory (depending on the variant and connected HW)

 

[AtenRa]

No?
None of the Promontory variants offer any PCIe Gen. 3 links, just up to 8 Gen. 2 links (X370) for general purpose. And those 8 Gen. 2 link require x4 Gen. 3 links from the CPU side.
Because there is plenty of other stuff in the IO extender too, the number of links it requires must be greater than just x4 Gen. 3 (I expect x8). And when the CPU has 32 links in total, that leaves 24 for other purposes (PCI-E & M.2).
Since Promontory offers up to 8 Gen. 2 links, you essentially get half of the links allocated by it back.

- So x32 Gen. 3 links in the CPU
- x8 Gen. 3 links connected to Promontory
- x24 Gen. 3 links left for GPP
- Up to 8 Gen. 2 links usable through Promontory (depending on the variant and connected HW)

Sorry im trying to understand what you two are talking,

ZEN CPU has 16x PCIe Gen 3.0 lanes + 4x PCIe Gen 3.0 lanes (SATA, M2.0 or even GPU for 3-way CF 8+8+4) + ZEN CPU will connect to the X370 via 4x PCIe Gen 3.0 lanes.
That makes 16+4+4 = 24 PCIe Gen 3.0 lanes, i dont understand why you say 8 lanes will be required for the CPU to Chipset connection.

edit: Are you saying the SERVER SKUs will connect to the Chipset via 8x PCIe Gen 3.0 lanes ??

 

[Atari2600]

Management and exec don't care and don't get involved in ANY of this. They focus on managing the guy below them, stakeholders and PR.

This attitude is why boardrooms are so often completely ineffectual! Folks seemingly don't understand what they should or should not be doing!

'Managing' the guy below them? What does that even mean? A load of bullshit bingo.


They make the big decisions - and right now in AMD there are no bigger decisions around than deciding how long to wait on respin refinements before bringing Zen to market. That decision will have went right to the top, even if only for confirmation of the opinion of the guy below.

 

[iBoMbY]

No?
None of the Promontory variants offer any PCIe Gen. 3 links, just up to 8 Gen. 2 links (X370) for general purpose. And those 8 Gen. 2 link require x4 Gen. 3 links from the CPU side.
Because there is plenty of other stuff in the IO extender too, the number of links it requires must be greater than just x4 Gen. 3 (I expect x8). And when the CPU has 32 links in total, that leaves 24 for other purposes (PCI-E & M.2).
Since Promontory offers up to 8 Gen. 2 links, you essentially get half of the links allocated by it back.

- So x32 Gen. 3 links in the CPU
- x8 Gen. 3 links connected to Promontory
- x24 Gen. 3 links left for GPP
- Up to 8 Gen. 2 links usable through Promontory (depending on the variant and connected HW)

Did you see any of the x370 slides from AMD?

Read the footnote 1 for example.

And the Ryzen sheet:

Where do you see your 32 PCIe lanes?

As far as I know it still looks exactly like this old picture:

Everything offered from Promontory shares a PCIe 3.0 x4 connection to the CPU. All that is missing from the picture is the option to convert the SATAe ports to PCIe 3.0 lanes.

Edit: Ups, was the wrong picture. Changed from Bristol Ridge to Summit Ridge.

Edit2: And to add to this, Marc Sauter, from German golem.de, who was at CES asked AMD, and they confirmed 24 PCIe lanes from Summit Ridge in AM4, from which 16+4 are usable, and 4 are for the chipset.

 

[The Stilt]

Did you see any of the x370 slides from AMD?



Read the footnote 1 for example.

And the Ryzen sheet:



Where do you see your 32 PCIe lanes?

As far as I know it still looks exactly like this old picture:



Everything offered from Promontory shares a PCIe 3.0 x4 connection to the CPU. All that is missing from the picture is the option to convert the SATAe ports to PCIe 3.0 lanes.

Edit: Ups, was the wrong picture. Changed from Bristol Ridge to Summit Ridge.

There are 32 PCIe lanes in the CPU, period.
If Promontory would connect to the CPU by using a x4 Gen. 3 link, how is it supposed to deliver x8 Gen. 2 (which is the same as x4 Gen. 3) simultaneously with USB3/3.1, SATA and eSATA?

AM4 is obviously not "FM3" either.

 

[CatMerc]

There are 32 PCIe lanes in the CPU, period.
If Promontory would connect to the CPU by using a x4 Gen. 3 link, how is it supposed to deliver x8 Gen. 2 (which is the same as x4 Gen. 3) simultaneously with USB3/3.1, SATA and eSATA?

AM4 is obviously not "FM3" either.

I imagine it will act like a network switch of sorts. It wouldn't need to provide full bandwidth for all devices at all times, that rarely happens. Intel does the same thing with their chipset.

 

[CentroX]

I'll bet they did. Over the past 3 months, AMD are essentially a one product company - they live or die on Zen.

Not really as they have Vega and Navi coming in their graphics department. But yes, Zen is important for them.

 

[ShintaiDK]

There are 32 PCIe lanes in the CPU, period.
If Promontory would connect to the CPU by using a x4 Gen. 3 link, how is it supposed to deliver x8 Gen. 2 (which is the same as x4 Gen. 3) simultaneously with USB3/3.1, SATA and eSATA?

AM4 is obviously not "FM3" either.

Z270 connects using PCIe 3.0 x4, yet it provides 24 lanes. PLX chips does the same, nothing new in this.

People are right when they tell you there is only 16+4(chipset)+2 or 4 depending on SATA configuration from the CPU. If you think there is 32, then document it.

 

[itsmydamnation]

Z270 connects using PCIe 3.0 x4, yet it provides 24 lanes. PLX chips does the same, nothing new in this.

So what your trying to say is Intel inherently have horrible over subscription on PCI when the CPU needs to access PCI devices?