New Transistor Technology
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I found an article with more details and a better explanation here at EETimes.Com.
Basing my conclusions only on the article and not any inside knowledge, essentially this is an SOI solution with three primary differences from what others (IBM and AMD) are using or are planning on using: this uses fully depleted SOI vs. the current partially depleted insulators, this uses a high-K dielectric (zirconium oxide, according to the EETimes) vs. traditional dielectrics, and this uses thicker source and drain terminals to offset the increased resistance from fully depleted SOI.
Basing my conclusions only on the article and not any inside knowledge, essentially this is an SOI solution with three primary differences from what others (IBM and AMD) are using or are planning on using: this uses fully depleted SOI vs. the current partially depleted insulators, this uses a high-K dielectric (zirconium oxide, according to the EETimes) vs. traditional dielectrics, and this uses thicker source and drain terminals to offset the increased resistance from fully depleted SOI.
<< I found an article with more details and a better explanation here at EETimes.Com.
So essentially this is an SOI solution with three primary differences from what others (IBM and AMD) are using or are planning on using: this uses fully depleted SOI vs. the current partially depleted insulators, this uses a high-K dielectric (zirconium oxide, according to the EETimes) vs. traditional dielectrics, and this uses thicker source and drain terminals to offset the increased resistance from fully depleted SOI. >>
Thanks.
Man... I'm an electrical engineer... and after reading your little post there.... I feel DUMB as rocks!! :disgust: The SOI lost me right away. UGH. After graduation... I went into semiconductor test engineering... and have been pretty distant from process technology, and I've totally forgotten how transistors work at the electron level (depletion regions, etc.). I probably use 1% of my scholastic knowledge to do my job... or at least I feel that way.
As far as losing knowledge, I have the same problem with control, power electronics as well as communications - I used to know a lot about control electronics and have lost it all through not really using it now that I specialize in CMOS design.
Again, the following is based on my prior research into SOI and the EETimes.Com article that I cited, and not on any knowledge of what Intel is actually planning on doing. I have not read the IEDM presentation and have no inside knowledge of the details of Intel's SOI plans.
Conventional silicon wafers use essentially a large, somewhat thick circular chunk of silicon as the starting platform that transistors are then created on top of. SOI is "Silicon On Insulator" and refers to a type of silicon wafer in which there is a somewhat thick chunk of silicon that forms the bulk of the wafer, on top of this there's a relatively thin insulator (referred to as the bulk oxide) and then on top of this a new layer of silicon is deposited (referred to as an epitaxial silicon layer, or epi layer). The transistors are created on top of this epi layer.
The only physical difference between fully depleted and partially depleted SOI is the thickness of the layers. Partially depleted uses a relatively thick layer of insulator followed by a relatively thick silicon layer. Fully depleted uses much thinner layers. The names come from the fact that the depletion region on fully depleted SOI reaches down all the way to the bulk oxide whereas in the partially depleted SOI, the depletion region ends and there is still some non-depleted silicon between the bottom of the transistor and the bulk oxide. To explain exactly what depleted silicon is would take some diagrams and some time. Suffice to say (and this is not debated in the industry, it is a fact): fully depeted SOI is better than partially depleted.
So why do people use partially depleted? It's a matter of complexity. Fully depleted SOI requires extremely tight manufacturing margins. You need to have very precise thicknesses to achieve the advantages that fully depleted can offer over partially, and this precision results in much higher cost. People (like myself) say that SOI is expensive, but this is in reference to partially depleted SOI which is the most common in use nowadays, fully depleted is quite a bit more expensive than even this. There is also concern that wafer manufacturers may have problems supplying high-quality, fully-depleted, completely planar (flat) SOI wafers in high volumes.
Switching to SOI reduces a form of leakage called subthreshold current (or Ioff) that occurs when a transistor is supposedly turned off. Fully depleted reduces this leakage even more than partially depleted. If you think of transistor current as being water that flows out of a water faucet depending on a signal (in this case the tap/handle of the faucet), subthreshold leakage is the equivalent of a leaky faucet that runs even when it's supposed to be off. It also has other benefits (it's faster, packing density is improved, etc.).
The other primary form of leakage is something called gate oxide leakage that is current that tunnels through the increasingly thin region that separates the gate from the channel of the transistor. If we go back to the faucet metaphor, it would be like the faucet sucking water out of your hand while your hand is on the tap. Gate leakage is a function of oxide thickness, and I discuss this in another post of mine in this thread. The thicker the oxide, the less likely it is that electrons can tunnel through the gate. But if you increase the oxide thickness while leaving everything else the same, you lose performance since the capacitance of the gate is reduced. So what you want is a way to maintain a value of gate capacitance while increasing the thickness of the gate. The easiest way to do this is to switch to a material in the gate that has a higher dielectric constant. So, the high-K dielectric tackles the other part of leakage by allowing higher thicknesses of dielectric while maintaining a given level of performance.
The third "new thing" offsets a disadvantage of fully depleted SOI - higher channel resistance. By increasing the thickness of the contacts of the source and drain you can reduce the resistance going into the transistor and can partially offset the increased channel resistance.
Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.
Again, the following is based on my prior research into SOI and the EETimes.Com article that I cited, and not on any knowledge of what Intel is actually planning on doing. I have not read the IEDM presentation and have no inside knowledge of the details of Intel's SOI plans.
Conventional silicon wafers use essentially a large, somewhat thick circular chunk of silicon as the starting platform that transistors are then created on top of. SOI is "Silicon On Insulator" and refers to a type of silicon wafer in which there is a somewhat thick chunk of silicon that forms the bulk of the wafer, on top of this there's a relatively thin insulator (referred to as the bulk oxide) and then on top of this a new layer of silicon is deposited (referred to as an epitaxial silicon layer, or epi layer). The transistors are created on top of this epi layer.
The only physical difference between fully depleted and partially depleted SOI is the thickness of the layers. Partially depleted uses a relatively thick layer of insulator followed by a relatively thick silicon layer. Fully depleted uses much thinner layers. The names come from the fact that the depletion region on fully depleted SOI reaches down all the way to the bulk oxide whereas in the partially depleted SOI, the depletion region ends and there is still some non-depleted silicon between the bottom of the transistor and the bulk oxide. To explain exactly what depleted silicon is would take some diagrams and some time. Suffice to say (and this is not debated in the industry, it is a fact): fully depeted SOI is better than partially depleted.
So why do people use partially depleted? It's a matter of complexity. Fully depleted SOI requires extremely tight manufacturing margins. You need to have very precise thicknesses to achieve the advantages that fully depleted can offer over partially, and this precision results in much higher cost. People (like myself) say that SOI is expensive, but this is in reference to partially depleted SOI which is the most common in use nowadays, fully depleted is quite a bit more expensive than even this. There is also concern that wafer manufacturers may have problems supplying high-quality, fully-depleted, completely planar (flat) SOI wafers in high volumes.
Switching to SOI reduces a form of leakage called subthreshold current (or Ioff) that occurs when a transistor is supposedly turned off. Fully depleted reduces this leakage even more than partially depleted. If you think of transistor current as being water that flows out of a water faucet depending on a signal (in this case the tap/handle of the faucet), subthreshold leakage is the equivalent of a leaky faucet that runs even when it's supposed to be off. It also has other benefits (it's faster, packing density is improved, etc.).
The other primary form of leakage is something called gate oxide leakage that is current that tunnels through the increasingly thin region that separates the gate from the channel of the transistor. If we go back to the faucet metaphor, it would be like the faucet sucking water out of your hand while your hand is on the tap.
Gate leakage is a function of oxide thickness, and I discuss this in another post of mine in this thread. The thicker the oxide, the less likely it is that electrons can tunnel through the gate. But if you increase the oxide thickness while leaving everything else the same, you lose performance since the capacitance of the gate is reduced. So what you want is a way to maintain a value of gate capacitance while increasing the thickness of the gate. The easiest way to do this is to switch to a material in the gate that has a higher dielectric constant. So, the high-K dielectric tackles the other part of leakage by allowing higher thicknesses of dielectric while maintaining a given level of performance.The third "new thing" offsets a disadvantage of fully depleted SOI - higher channel resistance. By increasing the thickness of the contacts of the source and drain you can reduce the resistance going into the transistor and can partially offset the increased channel resistance.
Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.
pm:
this is one of the most facinating and interesting things in the world to me, how do you become a microprocessor design engineer? what should i go for in graduate work? wold a doctorate be better? what's the demand in the feald? and what's the average pay?
this is one of the most facinating and interesting things in the world to me, how do you become a microprocessor design engineer? what should i go for in graduate work? wold a doctorate be better? what's the demand in the feald? and what's the average pay?
PM is damn good from what I am reading.
I don't think what Intel is announcing is so damn revolutionary, as much as evolutionary. Hi-K dielectrics have long been in development, and so has SOI.
BTW, if you are waiting for that 1 terahertz processor, don't hold your breath This is just how they can get a bunch of inverters to oscillate, not CPU clock speed. Also, SOI cost could be prohibitive for a long while.
PM, how is Fort Collins? How is job market holding up there?
I don't think what Intel is announcing is so damn revolutionary, as much as evolutionary. Hi-K dielectrics have long been in development, and so has SOI.
BTW, if you are waiting for that 1 terahertz processor, don't hold your breath
This is just how they can get a bunch of inverters to oscillate, not CPU clock speed. Also, SOI cost could be prohibitive for a long while.PM, how is Fort Collins? How is job market holding up there?
<< This is one of the most facinating and interesting things in the world to me, how do you become a microprocessor design engineer? >>
Probably the best formula that I can describe, would be something like: get a BSEE, keep your grades up above 3.0, preferrably 3.5 or better, get an internship with some big company doing something related to CPU design, get an MSEE and specialize in something related to microprocessors or CMOS logic.
<< what should i go for in graduate work? >>
Specialize in something related to CMOS, logic, process technology, or, (worst-case) software CAD for VLSI.
<< would a doctorate be better? >>
I find that, at Intel at least, it's harder to get a job with a doctorate unless you want to go into research. To get into design, a doctorate is argueably a liability unless you are a superstar. The pay scale for doctorates is so high that in most cases that I often I vote to skip them even if they interview well. We hire doctorates into design, but they have to be very good.
<< what's the demand in the field? >>
This is hard to quantify. From 1995-1999 I was getting (and I am not making this up) a headhunter call a week, sometimes two or three. I would get at least 45 a year. I have no idea how they got my number, but at least once a week someone would call and say "a friend has recommended that we contact you regarding an opportunity at a startup in <insert: San Jose, San Diego, Denver, Raleigh, Austin, Boston> working on the next generation microprocessor technology". And this wasn't just me, my co-workers and I would compare notes. If you'd received a patent, or published a paper, the call rate was even higher. So it was out of control for a while. Now, it's not impossible to find a job, but it's not easy either. For most people (unless you are in Silicon Valley), you'd probably need to move, but there are definitely openings for the right people. My site is currently hiring in specific fields.
<< and what's the average pay? >>
This is a tough question, not because I'm uncomfortable answering but because many high-tech companies are performance driven. A large percentage of my salary is in stock options and bonuses, so do you count those or not? If you do, then it's hard to guess their value... this year I'm not getting benefits from either of them. Base starting salary for a BS grad is probably somewhere around $65 or so I'd guess. With 7+ years of experience, $85k is probably average. But like I said this doesn't count bonuses or options, so in a good year you should add 10-20% more to these numbers to account for 'performance compensation'. Here's a link to the EETimes Salary Survey for 2001.
<< PM, how is Fort Collins? >>
It's a nice place to live. A nice place to raise a family. I like it. The weather isn't quite as nice as the small town that I grew up in Northern California, but it has a nice small town atmosphere while having all the advantages of a bigger city, and California cities either don't have the former or don't have any jobs for me.
<< How is job market holding up there? >>
It's ok, it could be worse considering. My company, Intel, is hiring here for experienced VLSI designers (email me if you know anyone who would be interested). I believe that Microsoft is hiring locally (they do hardware development in Fort Collins, I believe). The other big high-tech employers in town: HP, LSI Logic, Agilent, National Semiconductor, and Celestica are pretty much frozen, although if you have the right skillset it's probably possible to get a job at a couple of these.
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