new "Piledriver" x86 cores

[csbin]

We will likely see new revisions of Vishera with improved IMC's and improved power consumption/clockspeed

 

[inf64]

The "new" part obviously refers to changes from BD to PD,not "new" in a sense that they have changed something in PD itself. There is an algorithm change in the way how Turbo behaves and Richland will show tangible improvements over TN-A1 there. These are coupled with process node improvements GloFo has achieved. Similar goes for possible Vishera refresh( 8370 or whatever the name will be).

 

[Olikan]

The "new" part obviously refers to changes from BD to PD,not "new" in a sense that they have changed something in PD itself. There is an algorithm change in the way how Turbo behaves and Richland will show tangible improvements over TN-A1 there. These are coupled with process node improvements GloFo has achieved. Similar goes for possible Vishera refresh( 8370 or whatever the name will be).

there was changes...
amd CPU development is like GPUs, from GCN 1.0 to 2.0, they added the flat instruction + minor things

from trinity to vishera.... the "major" improvement was, be able to do 4, 64bit movs, instead of 2 per clock, in the AGU pipes...

and only do major changes when jumping nodes, 28nm kavery, 32nm VLIW-4*

* yes, vliw-4 shipped at 40nm, but was originally designed to be at 32

 

[csbin]

The "new" part obviously refers to changes from BD to PD,not "new" in a sense that they have changed something in PD itself. There is an algorithm change in the way how Turbo behaves and Richland will show tangible improvements over TN-A1 there. These are coupled with process node improvements GloFo has achieved. Similar goes for possible Vishera refresh( 8370 or whatever the name will be).

Richland "Piledriver" x86 cores

Vishera new "Piledriver" x86 cores

 

[inf64]

Richland "Piledriver" x86 cores

Vishera new "Piledriver" x86 cores

I'm just telling you know so you don't get disappointed later . New Vishera models won't have anything different than the old ones. Clock bump +process node tweaks are good for a new model name and +~5% more performance.

 

[Rvenger]

Lower leakage chips = higher clockspeed under same power envelope = more IPC through frequency. CMT design needs higher clocks to perform better so this is a good thing imo.

 

[inf64]

Lower leakage chips = higher clockspeed under same power envelope = more IPC through frequency. CMT design needs higher clocks to perform better so this is a good thing imo.

IPC(instructions per cycle) stays the same. Maybe you meant :
"higher clockspeed under same power envelope = more performance(or IPS*) through frequency"

*IPS=instructions per second and is equal to : (IPC x clock speed)