http://i.imgur.com/j4uv5oT.jpg
Looking at the slide it states up to two channels of memory. Implying, that most SKUs will be single channel. With the high-end models being dual channel.
===
- 1 MB L2 Excavator Module #1
- 1 MB L2 Excavator Module #2
- 1 MB L2 VI GCN CU Array #1
- 1 MB L2 VI GCN CU Array #2
The ring-based fabric interconnect with Hypertransport 4.0;
32 * 2(DDR) * 8 GHz => 64 GB/s
* 4 => 256 GB/s (I'm assuming 128-bits unidirectional)
Total peak aggregate of all L2 caches; 256 GB/s
^== My assumption for AMD's Hypertransport Fabric. That will be replacing the Crossbar that is SRI and System XBAR and GPU bi-XBAR.
^== We are looking at something like this. Since, that is QPI based and AMD's implementation is Hypertransport based.
It does seem weird for this to happen so late in the game. To switch from the three individual point to point interconnects to a single ring-based interconnect.
It should be noted it is a ring-based interconnect not an actual ring interconnect. So, it could be a star ring, or a 2D Torus mesh, or something like these.
Since the; GPUs and CPUs, L1s are write-through and the L2s inclusive. This increases the interconnectivity of the CPU and GPU products because of the Coherent Hypertransport fabric. The L3 cache and memory interface will be shared across all units because of the Hypertransport interconnect.
APUs and GPUs will be using this coherent Hypertransport ring-based interconnect.
If you don't want to look through my posts I'm talking about these;
http://www.linkedin.com/in/jeanchittilappilly
July 2012 Present (2 years 1 month)
Working on verifying AMD's coherent hyper transport fabric for Radeon & APU products
http://www.linkedin.com/pub/mike-osborn/10/586/797
March 2002 December 2012 (10 years 10 months)
Future Architectures: Architect/uArchitect
Key contributor to: Definition and documentation of a high density server fabric;
Definition of a Scalable Coherent SOC interconnect architecture for x86 and ARM based designs, including fabric protocol and interface definitions; Architecture, documentation, and implementation of a scalable ring-based transport. Led a design team responsible for uArch and implementation of both the protocol and transport layer of an AMD-ambidextrous SOC interconnect fabric.
Post your reply in here so we don't fill this topic up;
http://forums.anandtech.com/showthread.php?t=2390965&page=7
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