need help with timing diagram

[OS]

diagram

as you can see, variables decsel, RegA, RegB aren't lined up in the simulation output.

But in my stimulus file, they were supposed to be synced at the same time. Source for the stimulus is as follows;

initial
begin
enable = 1;
datain = 10; decsel = 0; RegA = 0; RegB = 0;
#1 datain = 2; #1 decsel = 1; #1 RegA = 1; #1 RegB = 1;
#1 datain = 4; #1 decsel = 2; #1 RegA = 2; #1 RegB = 2;



What gives?


source for model
source for stimulus

 

[Analog]

Show me a schematic, reading code is difficult. Are there any built - in propogation delays?

 

[OS]

Originally posted by: yellowfiero
Show me a schematic, reading code is difficult. Are there any built - in propogation delays?

I don't have a schematic, it's all written in Verilog. I don't know how propogation delays work out in Verilog unfortunately.

It seems to do what I'm looking for, but I'd like to know why it's different for each part. I guess it's a verilog specific issue.

 

[Analog]

well, you're delays are on the order of 1nS, so I'd say it must be some built-in propogation delay spec. I would look to see if you can turn that off. 1nS per gate isn't really that unusual, but it is device and logic family specific.

 

[etech]

What IC family has gate delays of 1nS? I'm ignoring ecl just because I've never had to work with it.

Is that internal gates or a device gate?

74LS gate delays or on the order of 10 to 15 nS.

74HC around 2- 4 nS.

74S might be around 1 but I don't have my databook on that family handy.

 

[FeathersMcGraw]

Are all of the entries on one line supposed to be some sort of parallel signal assertion syntax? Because (keeping in mind that any Verilog experience that I might have had disappeared years ago) it sure looks like you get 1ns of delay between each assertion.

Alternatively, switch the stimulus declarations for RegA and RegB (so RegB is asserted first) and see if the delay for those signals is reversed. If so, there might be some other syntax you're missing to do input line assertions "at the same time".

 

[Analog]

Originally posted by: etech
What IC family has gate delays of 1nS? I'm ignoring ecl just because I've never had to work with it.

Is that internal gates or a device gate?

74LS gate delays or on the order of 10 to 15 nS.

74HC around 2- 4 nS.

74S might be around 1 but I don't have my databook on that family handy.

ECL logic.

 

[OS]

Originally posted by: FeathersMcGraw
Are all of the entries on one line supposed to be some sort of parallel signal assertion syntax? Because (keeping in mind that any Verilog experience that I might have had disappeared years ago) it sure looks like you get 1ns of delay between each assertion.

Alternatively, switch the stimulus declarations for RegA and RegB (so RegB is asserted first) and see if the delay for those signals is reversed. If so, there might be some other syntax you're missing to do input line assertions "at the same time".

This was half of my problem, the other half was that I was using blocking assignments when I should have used nonblocking. I'm such a freaking moron.

Anyways this is what it's supposed to look like

thanks all