NAND scaling in the future (How do you think it will affect future pricing?)

[cbn]

According to the following article hitting 128 layers for 3D NAND will be difficult:

http://semiengineering.com/whats-next-for-nand/

What’s Next For NAND?

Vendors pin hopes on 3D memory, raising specter of 2D NAND shortages; other memory types add to uncertainty.

May 19th, 2016 - By: Mark LaPedus

NAND flash memory is a key enabler in today’s systems, but it’s a difficult business. NAND suppliers require deep pockets and strong technology to survive in the competitive landscape. And going forward, vendors face new challenges on several fronts.

On one front, for example, the overall NAND market is currently in the doldrums, amid soft product prices and a mild capacity glut. Demand is expected to rebound in the second half of 2016, although there is still uncertainty in the market.

Then, on the technology front, today’s planar NAND is reaching its physical scaling limit. And so NAND suppliers are pinning their future hopes on the successor to planar NAND—3D NAND.

3D NAND is shipping, but the technology is taking longer than expected to enter the mainstream. It is more difficult to make than previously thought. 3D NAND resembles a vertical skyscraper, in which horizontal levels or layers are stacked and then connected using tiny vertical channels.

“The early movers, such as Samsung and Micron, are ramping up 3D NAND quickly, while SK Hynix and SanDisk/Toshiba are lagging,” said Greg Wong, an analyst with Forward Insights. “The technology and yield learning is taking longer.”

And it isn’t getting any easier. Today’s leading-edge 3D NAND chips are 32- and 48-layer devices, but the technology will likely hit the ceiling at 128 layers in the 2018 timeframe or so. So to extend 3D NAND beyond 128 layers, vendors are quietly developing a technology called string stacking. Still in R&D, string stacking involves a process of stacking individual 3D NAND devices on top of each other.

For example, a vendor might stack three separate 48-layer 3D NAND devices, creating a 144-layer chip. Even with string stacking, though, 3D NAND could hit the wall at 300 layers. It will take vast resources and capital to extend current and futuristic 3D NAND devices to 128 layers and beyond. “Scaling the number of layers is not just a technical challenge, but an economic one as well,” Wong said.

In any case, OEMs will need to keep close tabs on the technology. To help OEMs, Semiconductor Engineering has taken a look at the status of the following technologies—planar NAND; 3D NAND; and futuristic 3D NAND with string stacking.

Planar NAND
Invented in the 1980s, NAND flash is a nonvolatile memory technology that can be electrically erased and reprogrammed. Basically, NAND is used for data storage applications. Its close cousin, NOR flash, is geared for code storage. In today’s systems, NAND plays a key role in the traditional memory hierarchy. Basically, SRAM is integrated into the processor for cache. DRAM is used for main memory. And disk drives and NAND-based solid-state drives (SSDs) and memory cards are used for storage.

The NAND market is dominated by large suppliers. (See chart below.)


Source: Semiconductor Engineering chart compiled from TrendForce data.

In 2015, worldwide NAND revenues increased by 10%, while bit growth grew by 52%, according to Web-Feet Research. “In 2016, revenue will be flat at a 0.4% growth rate even though bit growth will come in around 46%,” said Alan Niebel, president of Web-Feet Research. “This is due to oversupply of planar NAND and price declines for mobile, consumer and some SSDs.”

Today, prices for planar NAND are inexpensive and continue to fall. Not long ago, for example, hard disk drives (HDDs) were significantly cheaper than rival NAND-based SSDs. By year’s end, the price difference between a 128-GB SSD and a 500-GB HDD will fall to less than $3, according to TrendForce.

For OEMs, though, there is a potential problem. NAND flash vendors have converted some of their planar NAND fab capacity over to 3D NAND. If demand picks up, and vendors can’t ramp up 3D NAND fast enough, OEMs could face product shortages in the second half of 2016 and perhaps beyond.

“Our outlook is for a shortage in NAND in general,” said Jim Handy, an analyst with Objective Analysis. “It all depends on whether or not people are able to overcome the technical barriers to get out 3D NAND. And it’s really hard to predict when that will happen.”

The other problem? Planar NAND is running out of steam.

Planar NAND is running out of steam, but it’s far from dead.
Planar NAND is based on a floating gate transistor structure. A NAND device, which resembles a MOSFET, consists of a source and a drain with a channel running between them. Unlike a MOSFET, there are two gates on the top of a NAND structure. A control gate is on top, while the floating gate is on the bottom. The two gates are insulated by an oxide layer.

The data is stored in a NAND cell. In single-level cell (SLC) NAND flash, there is 1 bit of data per cell. Today’s mainstream NAND makes use of multi-level cell (MLC) and triple-level cell (TLC) technology, which stores 2 bits and 3 bits of data per cell, respectively.

NAND vendors have scaled the cell size by roughly 100 times over the past decade, according to Micron Technology. In fact, thanks to advanced lithography, vendors have extended planar NAND down to the mid-1xnm node regime.

Today, NAND vendors are shipping 16nm and 15nm parts. But at those nodes, NAND is running of out of gas and it will no longer scale. It is becoming difficult to scale the memory cell and floating gate in planar NAND.

But planar NAND is not dead. “Planar NAND is not going away,” said Kevin Kilbuck, director of NAND strategic planning at Micron. “Customers want 2D NAND for the foreseeable future for let’s call it the non-high capacity storage market. Not all of the applications are moving to 3D NAND right away. And not all of the manufacturers will convert all of their capacity from 2D to 3D NAND overnight. It’s not economical to manufacture low-density products in 3D NAND fabs. It’s also very expensive to build new 3D NAND fabs or covert 2D NAND fabs to 3D.”

3D NAND
Still, the future rests with 3D NAND. This technology first appeared in 2007, when Toshiba introduced the world’s first 3D NAND technology. Later, Samsung, SK Hynix and the Micron/Intel duo introduced 3D NAND.

3D NAND represents a radical departure from planar or 2D NAND. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.

In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Basically, 3D NAND involves a stack of layers. The layers are connected with tiny vertical channels. The layers, which are horizontal, are the active wordlines. “The bitlines also run horizontally in the metal layers on the top of the chip,” Objective Analysis’ Handy said. “The vertical channels are the NAND ‘strings’ that attach to the bitlines.”

There are other differences as well. Micron and its technology partner, Intel, extended the floating gate architecture to 3D NAND. In contrast, Samsung, SK Hynix and the SanDisk/Toshiba duo are not using a floating gate for 3D NAND. Instead, these vendors went to a technology called charge trap flash.

All told, 3D NAND has some advantages over planar NAND. “Compared to planar NAND, 3D NAND offers a significant bit density increase,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research. “As such, there is increasing adoption of 3D NAND by SSDs as a storage solution for servers/datacenters as well as high-end consumer applications.”

Still, 3D NAND has some challenges. “From the device side, it’s the channel mobility,” said Er-Xuan Ping, managing director of memory and materials within the Silicon Systems Group at Applied Materials. “Polysilicon does not have good mobility.”

In 3D NAND, the goal is to move the current through a polysilicon-based vertical channel. A 3D NAND device with fewer layers, and a shorter channel length, might have acceptable mobility.

Problems can arise as vendors scale their devices with more layers, meaning the channel length becomes taller. “When you go up, the polysilicon channel will be limited by its mobility,” Ping said.

Mobility is affected by the number of layers.
In addition, 3D NAND involves a number of new and complex process steps in the fab. Planar NAND is dependent on advanced lithography. In contrast, 3D NAND makes use of trailing-edge geometries from 40nm to 20nm. 3D NAND requires lithography, but the challenges shift from advanced patterning to deposition and etch.

Despite the challenge, 3D NAND is set to take off. In 2015, the overall 3D NAND market reached $4.5 billion in terms of sales, according to Web-Feet Research. “In 2016, 3D NAND will come in big time with both Toshiba and Micron producing volume shipments, thereby growing worldwide bit shipments by 350% and revenues by 230%,” Web-Feet Research’s Niebel said.

Each vendor, meanwhile, is ramping up 3D NAND at various stages. In 2013, Samsung shipped the world’s first 3D NAND device, a 24-layer, 128-gigabit (Gb) chip. Then, last year, Samsung shipped its third-generation 3D NAND device. The device is 48 layers, based on tri-level cell (TLC) technology, resulting in a 256-Gb chip.

Samsung’s previous chip was a 32-layer chip. The 48-layer device is roughly 2X to 2.2X faster in terms of a sequential read and a sequential write, according to Jim Elliott, corporate vice president of Samsung Semiconductor.

The 48-layer chip also enables Samsung to penetrate new markets, namely the enterprise SSD sector. “The big story is TLC in the enterprise space,” Elliott said at the time of the product announcement, which was last year. “That’s where that disruption is taking place.”

Samsung’s rivals, however, opted to skip the 24-layer regime. For most, a 16nm or 15nm planar NAND chip is still cheaper on a cost-per-bit basis than a 24-layer 3D NAND device.

Meanwhile, the Intel/Micron duo recently entered the 3D NAND market by rolling out a 32-layer device. Meanwhile, SK Hynix and the SanDisk/Toshiba duo are separately sampling 48-layer products.

The 32-layer device from Intel/Micron supports both multi-level cell (MLC) and TLC technology, enabling densities of 256- and 384-Gb, respectively. The 384-Gb chip, according to Micron, is the highest density 3D NAND device in the market.

To accomplish this feat, Micron integrated the logic circuitry under the layer stack. It refers to this as CMOS under array. “We can get the majority of logic under the array, thereby saving a lot of space. That allows more density in a given silicon area,” Micron’s Kilbuck said. “It also allows us to segment the array. It can increase the number of planes, for example. Our NAND pages are divided into four planes. What that does is increase your throughput and performance of an individual die.”

Despite the obvious benefits of 3D NAND, there is one big question: When will 3D NAND reach price parity with 2D NAND?


Today, 3D NAND is sold at a premium. The 32- and 48-layer devices are inching closer in terms of price parity with 2D NAND. But it may take chips with 64 layers and beyond to reach the magical price parity point.

“Our TLC-based 3D NAND is getting close to what 2D MLC can do in endurance,” Kilbuck said. “My gut feeling is sometime next year we would see price parity between 2D and 3D. I’m talking about price per gigabyte. But everybody needs to be in high volume (production) for that to occur.”

What’s next?
So what happens next? “This is the year of 48 layers going to 64,” Applied’s Ping said. “Whether 3D NAND can go to 96 or 128 is limited by the etching capability.”

In fact, it’s difficult to fabricate devices with 64 or more layers. Right now, the high-aspect ratio etch tools are not ready or struggling to fabricate devices at 64 layers and beyond. For now, the aspect ratios are too complex and difficult.

And at 64 layers and beyond, channel mobility becomes an issue, as previously stated. “It will limit the device performance or device height,” Ping said.

So going forward, NAND suppliers will simultaneously follow two parallel paths. The first path is to wait for the etch tools and other manufacturing techniques to arrive. And if they arrive on time, vendors could scale today’s 3D NAND device from 32- and 48-layers, to 64 layers, to 96 and then to 128.

The second path is to move towards string stacking technology. This involves stacking two or more individual devices on top each other. Each device is separated by an insulating layer.

String stacking is already in the works. Recently, Micron presented a paper on a new 64-layer chip. Micron, according to multiple sources, stacked two 32-layer chips on top of each other.

In theory, string stacking could involve several different combinations. For example, a vendor could stack three 32-layer chips, enabling a 96-layer device. In addition, a vendor could stack three 96-layer chips, resulting in a 288-layer product.

The trick is to connect the various chips together. Today, vendors are looking at several different interconnect schemes. “Some of them will put a source line in the middle,” Ping said. “That is just one of the many options.”

Clearly, string stacking is challenging. And even with this technology, 3D NAND could hit the wall at 300 layers or so. “That’s the limit,” he said. “That’s based on yield and stress.”

All told, 3D NAND will remain viable at least to 2020, and perhaps beyond. But suddenly, 3D NAND has some new competition, which complicates the landscape.

Today, the Intel/Micron duo are sampling 3D XPoint, a ReRAM-like device that could potentially compete with 3D NAND in enterprise SSD applications. ReRAM, a nonvolatile memory technology, is attractive because it delivers fast write times with more endurance than today’s flash.

There are other promising technologies in R&D, particularly vertical ReRAM. “The densities (in vertical ReRAM) won’t be as high as 3D NAND,” Ping said. “But the speeds can overcome some of these density limitations.”

Time will tell if ReRAM will displace 3D NAND. In fact, ReRAM and the other next-generation memory types still have a lot to prove. At one time, the newfangled memory types were supposed to replace conventional memory, but they have fallen short of their promises. And conventional memory, such as DRAM and NAND, continue to chug along.

....So assuming 3D NAND production improves do we eventually see the NAND market become like the hard drive market? This where the low capacity drives stagnate in price and the only gains happen at the top end from increasing the capacity of each drive?

For example, with the string stacking mentioned in the article, I don't see that reducing the cost of manufacture. It just makes it possible to increase the capacity of each drive.

 

[cbn]

Here is the Seagate Hard drive pricing I remember observing for at least the past ~3 years:

1TB = $50
2TB= $70
3TB= $90

Does the SATA 6 Gbps SSD market become similar in that drive prices at certain capacity level don't drop anymore? If so where do you think 3D TLC prices will stabilize for 240/256GB, 480/512GB, 960/1024GB? (Will there even be a 120/128GB?)

 

[VirtualLarry]

I'm still holding out for a 3D NAND 240GB SSD for $40 USD, "new". They've been as low as $60 on a good sale. (As were the PNY CS1111 240GB BX100-clone SM2246EN MLC drives, from BestBuy on ebay, until they sold out of them. I managed to snag a couple.)

 

[cbn]

According to the following article Toshiba's 64 layer NAND will be 512Gb (64GB) TLC:

http://www.anandtech.com/show/11142/toshiba-samples-64layer-512-gb-bics-3d-nand

And Micron's 64 layer NAND will be will be 512Gb (64GB) and 256Gb (32GB):

http://www.anandtech.com/show/11100...ce-roadmap-updates-forecasts-and-ceo-retiring

With the second generation 3D NAND, Micron is shifting their strategy slightly by offering at least two different die sizes. We've previously heard about the 512Gb 64-layer 3D TLC part, but Micron will also be making a smaller 256Gb 3D TLC part. This die is planned to be the smallest 256Gb NAND flash die available from any vendor, at 59 mm^2 or 4.3Gb/mm^2. The smaller die is intended for the mobile market where the 512Gb part will be physically too large.

So 96 layer TLC would be 768Gb (96GB) assuming die sizes are the same. However, I do wonder if the die size at 96 layer will grow prior to proceeding to 128 layer (due to 128 layer being extremely difficult according to the article in the opening post).

 

[cbn]

I'm still holding out for a 3D NAND 240GB SSD for $40 USD, "new".

That shouldn't be hard to accomplish (eventually). I just wonder how much lower it could go?

 

[cbn]

Here is a prediction I will make for 3D TLC SATA 6 Gbps SSDs (with a good controller):

120/128GB: $25
240/256GB: $35
480/512GB: $55
960/1024GB: $95

Not sure when this will happen though? At the end of the 64 layer 3D TLC NAND generation? Or later than this?

 

[cbn]

Samsung expects 512 GB SSDs to cost the same as 1TB HDD in 2020:

https://www.overclock3d.net/news/st..._ssds_to_cost_the_same_as_a_1tb_hdd_in_2020/1

Samsung now expects 512GB SSDs to cost the same as a 1TB HDD in 2020, promising price reductions of over 50% over the 3-4 years.

Since 2012 Samsung has already decreased the price of their 512GB SSDs by 69%, reducing the cost/GB from $1.17 per GB to just $0.36 per GB. Right now it is expected that 256GB SSDs will hit price parity with 1TB HDDs between 2017 and 2018.

 

[cbn]

So according to the previous post we would have $50 512GB SSDs by 2020.

So would that be based on mature 64 layer TLC or earlier yield 96 layer TLC?

If based on mature 64 layer TLC then I would assume by the time 96 layer TLC matures 768GB SSDs would be $50. (re: 96 layers is 50% more than 64 layers and thus the capacity at the $50 SSD level would also grow by 50%. Therefore 512 GB @ $50 becomes 768GB @ $50).

 

[BSim500]

So according to the previous post we would have $50 512GB SSDs by 2020.

You're assuming they'll actually pass on nearly all of the cost savings to the consumer. Even before 3D NAND, Samsung's TLC 840 EVO's used to cost the same as Crucial's MLC MX100/200's at same capacity & lithography for no real reason other than premium branding, and even today Samsung 850 EVO's are +20% up on MX300's in many regions (and Samsung 850 EVO's V2 48-layer are no real cheaper than V1 32-layer).

MLC to TLC is a one-shot gain (trying to push into 4-bit QLC, etc, is highly undesirable from a durability perspective with P/E cycles falling into the hundreds rather than thousands, requiring even more complex controllers and multiple layers of error correction (which is half the reason TLC isn't that much cheaper than uncached MLC), more frequent background refreshing (making actual P/E cycles look even worse) and unpowered data retention probably weeks rather than months). The only real option is 3D layer scaling, and whilst it's interesting to speculate how far they can push that, I'll believe the economic impact of that when I see actual price cuts at the consumer end, as a 30% cut in manufacturing costs sure as hell doesn't translate to a 30% drop in end consumer prices for many businesses.

 

[cbn]

You're assuming they'll actually pass on nearly all of the cost savings to the consumer.

If you click on that link in post #7.....Samsung claims a history of strong retail price reductions though. Of course, cost of manufacture may (and probably is) different than the retail price reduction.....but that is not what they are referring to when they make their example.

Since 2012 Samsung has already decreased the price of their 512GB SSDs by 69%, reducing the cost/GB from $1.17 per GB to just $0.36 per GB.

 

[Glaring_Mistake]

MLC to TLC is a one-shot gain (trying to push into 4-bit QLC, etc, is highly undesirable from a durability perspective with P/E cycles falling into the hundreds rather than thousands, requiring even more complex controllers and multiple layers of error correction (which is half the reason TLC isn't that much cheaper than uncached MLC), more frequent background refreshing (making actual P/E cycles look even worse) and unpowered data retention probably weeks rather than months).

Don't need to wait for QLC to see SSDs with just a few hundred P/E cycles since both SanDisk Ultra II and the 750 EVO have around 500 P/E cycles.
According to Billy Tallis (or possibly Kristian Vättö) 3D QLC is supposed to be fairly equivalent to 2D TLC around 15nm and even that can hold up to voltage drift fairly well if paired with a competent controller despite not doing a lot of rewrites.

Also, BSim500, I came across your thread over on the Crucial forums asking for information on how much the MX300 looks to suffer from voltage drift (where I did my share by posting an early test of an MX300 with SSDRST).
But since you haven't commented after that I can't tell whether you've seen the updates to your thread.

 

[BSim500]

If you click on that link in post #7.....Samsung claims a history of strong retail price reductions though. Of course, cost of manufacture may (and probably is) different than the retail price reduction.....but that is not what they are referring to when they make their example.

I paid around 5% more for a 256GB Samsung 830 (20nm MLC?) around 2011-2012 vs an MX100 500GB (16nm MLC) in 2014. A clear doubling in GB/$ over 2 years agrees that Samsung's 69% claim is accurate. But the key issue is "past (2011-2015) performance is not indicative of future (2017-2021) scaling". Nearly all of the $600 to $240 price falls for 500GB capacity Samsung claimed occurred during the earlier 2011-2015 years going from 32nm to 16nm. 2015-2017 pricing has been very stagnant even with 32 -> 48 layers, and I'm not really seeing any significant 2011-2016 falls that can reasonably be "extrapolated" into a similar continuous straight line from 2017-2022.

As mentioned, the real "boost" was the one-off MLC -> TLC mainstream transition, not the actual 3D-ness vs planar. Compare MLC vs MLC and price "evolution" since 2015 has been abysmal. Same goes with NVMe, it's going to take a 30% haircut just to tread water with SATA at same capacity. I hope adding more 3D layers does scale well, because it if doesn't, unless NAND technology itself gets replaced by a "game-changer", the date upon which we reach HDD price parity will be "The Twelfth of Never".

Don't need to wait for QLC to see SSDs with just a few hundred P/E cycles since both SanDisk Ultra II and the 750 EVO have around 500 P/E cycles. According to Billy Tallis (or possibly Kristian Vättö) 3D QLC is supposed to be fairly equivalent to 2D TLC around 15nm and even that can hold up to voltage drift fairly well if paired with a competent controller despite not doing a lot of rewrites.

Hey thanks for your reply Glaring Mistake! I haven't been following the thread but the drive does seem to be holding up a lot better than the BX200. As usual, it's pathetic "proper" tech sites still aren't even bothering to test slowdowns over time / data retention issues. As for QLC, at a mere sub 500 P/E cycles it becomes more about lack of confidence than tech specs (like a PSU with sh*tty capacitors some things just aren't worth it at any price), and personally I wouldn't touch QLC with a barge-pole. For unpowered backup drives, I'm still very wary even of TLC.

 

[imported_jjj]

NAND and DRAM prices are more a matter of supply vs demand than costs.
If supply growth trails behind demand growth like today, prices go up.
Medium term there is scaling and 4 bits per cell but scaling will slow down and might even stop at some point.
In 2018-2019 we'll start seeing Xpoint and 3D ReRAM and those will slowly replace NAND, starting with high end.
There might be some other technologies in the next decade that aim to be cheaper than NAND at similar perf.

 

[cbn]

Nearly all of the $600 to $240 price falls for 500GB capacity Samsung claimed occurred during the earlier 2011-2015 years going from 32nm to 16nm. 2015-2017 pricing has been very stagnant even with 32 -> 48 layers, and I'm not really seeing any significant 2011-2016 falls that can reasonably be "extrapolated" into a similar continuous straight line from 2017-2022.

I think once Toshiba/Sandisk (WD) and SK Hynix get their 3D NAND into full scale production will see another wave of price drops. Until that happens Samsung (and now Micron) enjoy a manufacturing advantage.

 

[Elixer]

I think once Toshiba/Sandisk (WD) and SK Hynix get their 3D NAND into full scale production will see another wave of price drops. Until that happens Samsung (and now Micron) enjoy a manufacturing advantage.

Add TSMC into the mix, they are going to buy some of Toshiba's NAND factory.

In addition, TSMC could be Toshiba's best production partner, as the foundry will help Toshiba expand its business in the 3D NAND field, the sources said. The partnership between TSMC and Toshiba could also pose a challenge to the longtime industry leader Samsung, which usually has sufficient profits generated from its memory business to subsidize its logic IC unit, the sources noted.

http://www.digitimes.com/news/a20170301PD206.html

 

[Glaring_Mistake]

Hey thanks for your reply Glaring Mistake! I haven't been following the thread but the drive does seem to be holding up a lot better than the BX200. As usual, it's pathetic "proper" tech sites still aren't even bothering to test slowdowns over time / data retention issues.

Yes, it looks to be much improved over the BX200.
Have run tests after that that I could upload on the Crucial forums if you want but they could probably be summed up by saying that: While voltage drift may still be a factor results still look fairly stable.

 

[cbn]

A really good follow-up article on the topic:

https://semiengineering.com/3d-nand-race-faces-huge-tech-and-cost-challenges/

Some quotes I liked...

Today, suppliers are ramping up 96-layer 3D NAND. For example, a 96-layer device from the Toshiba-Western Digital duo is a 512Gbit device with bit densities of 5.95Gbit/mm2. In comparison, a 64-layer is a 256Gbit device with a die size of 75.2mm2 and a bit density of 3.40Gbit/mm2.


The next technology on the roadmap is 128 layers, which is due out by year’s end. Recently, Toshiba-WD described the world’s first 128-layer device, a triple-level-cell 512Gbit product with a bit density of 7.80Gbit/mm2. “128 might be possible this year, at the end of the third or early fourth quarter of this year, although this is a custom sample but not mass production. Mass production should be early next year. Then, you have 192. That might be three stacks,” TechInsights’ Choe said.

Single deck vs. string stack vs. die stacking....

To make 3D NAND, suppliers have several options. One of the first manufacturing decisions is to determine which scaling approach is the best path. For this, there are two approaches—single deck or string stacking.


In a 96-layer device, some are stacking all 96 layers on the same chip. This is referred to as the single-deck approach. Others are using string stacking. For example, in a 96-layer device, some are stacking two 48-layer devices on top of each other, which are separated with an insulating layer.


In the fab, string stacking is a relatively easier approach. In string stacking, though, a vendor is making two devices. In effect, the vendor is doubling the number of steps, which translates into cost and cycle time.


“Companies have different strategies. Some would rather go with existing equipment and then do multi-tier integration. Multi-tier integration requires more process steps, but they can come to the market quickly. Single-tier can save the number of process steps, but developing such equipment and processes will take a little bit of time,” said Gill Lee, managing director of memory technology at Applied Materials.


At 128 layers, vendors will use both approaches. Most will stack two 64-layer devices on each other. In contrast, Samsung plans to use the single deck approach for 128 layers.


For now, 128 layers represent the limit for the single deck approach unless the industry comes up with a new breakthrough. So string stacking will become the norm beyond 128.


Beyond 128 layers, some vendors may stack two or more devices. For 192-layer devices, which are due out in 2021, vendors could string stack three 64-layer devices, according to TechInsights’ Choe.


String stacking won’t last forever and could run into issues at 500 layers. At this point, vendors are exploring another approach—die stacking. “It’s kind of a die-on-die approach,” Choe said.

This involves stacking 3D NAND dies, which are connected using through-silicon vias (TSVs), he said. Wafer bonding is another approach. In theory, using these approaches, the industry could stack a 500-layer die on top of another one, and so on.

 

[IntelUser2000]

If based on mature 64 layer TLC then I would assume by the time 96 layer TLC matures 768GB SSDs would be $50. (re: 96 layers is 50% more than 64 layers and thus the capacity at the $50 SSD level would also grow by 50%. Therefore 512 GB @ $50 becomes 768GB @ $50).

That assumes the cost is entirely based on NAND, and there's no overhead going to 96 layers.

At low prices like $50, other costs dominate. You could sell a drive where it has zero NAND chips, but it still has a DRAM buffer, a controller, PCB and the casing.

Also 96 layers are more complicated, so it'll take many years to get the full gains. Even then, it won't be on the low end. You don't see HDDs under $40 for the same reason, because there's the fixed cost that can't be reduced.

What more layers allow to do is increase capacity at the top end.

 

[cbn]

That assumes the cost is entirely based on NAND, and there's no overhead going to 96 layers.

At low prices like $50, other costs dominate. You could sell a drive where it has zero NAND chips, but it still has a DRAM buffer, a controller, PCB and the casing.

Also 96 layers are more complicated, so it'll take many years to get the full gains. Even then, it won't be on the low end. You don't see HDDs under $40 for the same reason, because there's the fixed cost that can't be reduced.

What more layers allow to do is increase capacity at the top end.

Agree with everything you wrote.

In fact, the article (written May 23rd 2019) I linked in post #17 indicated there is quite a bit of overhead when going to 96L.

P.S. Very interesting the "die stacking" mentioned by the article in post #17:

String stacking won’t last forever and could run into issues at 500 layers. At this point, vendors are exploring another approach—die stacking. “It’s kind of a die-on-die approach,” Choe said.

This involves stacking 3D NAND dies, which are connected using through-silicon vias (TSVs), he said. Wafer bonding is another approach. In theory, using these approaches, the industry could stack a 500-layer die on top of another one, and so on.

 

[cbn]

With the following critcism of high end capacity SSDs noted by Anandtech here I do wonder how soon high end application of NAND will be DIMMs.

DIMMs not because they would offer much of latency advantage (for NAND) but rather the higher bandwidth would offer the advantage of faster RAID rebuild times.

With that mentioned, the following caveat was written in the Anandtech post:

I was told that sure, drives above 16TB do exist in the market, however aside from niche applications (such as risk is an acceptable factor for higher density), volumes are low. This inflection point, one would imagine, is subject to change based on how the nature of data and data analytics will change over time.

That and PCIe 5.0 is around the corner.