My VHDL won't synthesize!

[beer]

So here is what I am trying to do:
Build an 8x4-bit wide array of delay registers. Three multiplexors select three of the registers, based on the opcode driven by selectlines SR1, SR2, and DR, and pass them out of the component. It's Pretty basic. Here is the code that is breaking: (Why doesn't HT have the 'attach code' feature?')

The source of the problem is the array instantiation. It works fine in simulation but below I past the problems I get in synthesis.


---------------RegisterFile---------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RegisterFile is
port(SR1, SR2, DR: in std_logic_vector(2 downto 0);
DR_data: in std_logic_vector(3 downto 0);
WE: std_logic_vector(7 downto 0);
CLK, RegSet, RegReset: in std_logic;
RegOutDr, RegOut1, RegOut2: out std_logic_vector(3 downto 0));
end RegisterFile;

architecture MixedDescription of RegisterFile is

component Register4
port(D: in std_logic_vector(3 downto 0);
WE, clk, RegSet, RegReset: in std_logic;
Q: inout std_logic_vector(3 downto 0));
end component;

type atex4BITARRAY is array (7 downto 0) of std_logic_vector(3 downto 0);
signal Q_array: atex4BITARRAY;

begin
RegFile8: for i in 0 to 7 generate
begin
Regx: Register4 port map (DR_DATA, WE(i), clk, RegSet, RegReset, Q_array(i));
end generate RegFile8;

process(SR1, Q_array)
begin
case SR1 is
when "000" =>
RegOut1 <= Q_array(0);
when "001" =>
RegOut1 <= Q_array(1);
when "010" =>
RegOut1 <= Q_array(2);
when "011" =>
RegOut1 <= Q_array(3);
when "100" =>
RegOut1 <= Q_array(4);
when "101" =>
RegOut1 <= Q_array(5);
when "110" =>
RegOut1 <= Q_array(6);
when "111" =>
RegOut1 <= Q_array(7);
when others => null;
end case;
end process;

process(SR2,Q_array)
begin
case SR2 is
when "000" =>
RegOut2 <= Q_array(0);
when "001" =>
RegOut2 <= Q_array(1);
when "010" =>
RegOut2 <= Q_array(2);
when "011" =>
RegOut2 <= Q_array(3);
when "100" =>
RegOut2 <= Q_array(4);
when "101" =>
RegOut2 <= Q_array(5);
when "110" =>
RegOut2 <= Q_array(6);
when "111" =>
RegOut2 <= Q_array(7);
when others => null;
end case;
end process;

-- Process to output the destination register contents to RegOutDR
process(DR, Q_array)
begin
case DR is
when "000" =>
RegOutDR <= Q_array(0);
when "001" =>
RegOutDR <= Q_array(1);
when "010" =>
RegOutDR <= Q_array(2);
when "011" =>
RegOutDR <= Q_array(3);
when "100" =>
RegOutDR <= Q_array(4);
when "101" =>
RegOutDR <= Q_array(5);
when "110" =>
RegOutDR <= Q_array(6);
when "111" =>
RegOutDR <= Q_array(7);
when others => null;
end case;
end process;

--Process to write data into the register file
process(CLK)
begin
if clk'event and clk = '1' then
for i in 0 to 7 loop
Q_array(i) <= DR_Data;
end loop;
end if;

end process;
end MixedDescription;



Now, in synthesis, I get the following error:

Synthesizing Unit <registerfile>.
Related source file is c:/engineering/xilinx/bin/mips_core/../../../SOURCE/PRegisterFile.vhd.
Register <Q_array<1>> equivalent to <Q_array<0>> has been removed
Register <Q_array<2>> equivalent to <Q_array<0>> has been removed
Register <Q_array<3>> equivalent to <Q_array<0>> has been removed
Register <Q_array<4>> equivalent to <Q_array<0>> has been removed
Register <Q_array<5>> equivalent to <Q_array<0>> has been removed
Register <Q_array<6>> equivalent to <Q_array<0>> has been removed
Register <Q_array<7>> equivalent to <Q_array<0>> has been removed
Found 4-bit 8-to-1 multiplexer for signal <RegOutDr>.
Found 4-bit 8-to-1 multiplexer for signal <RegOut1>.
Found 4-bit 8-to-1 multiplexer for signal <RegOut2>.
Found 4-bit register for signal <Q_array<0>>.
Summary:
inferred 4 D-type flip-flop(s).
inferred 12 Multiplexer(s).
Unit <registerfile> synthesized.

It's removing those signals. It shouldn't be. Is there another way to achieve the same ends? Appreciate any advice!

 

[TuxDave]

Can you copy and paste the lines which generates values for Q_array(0) and Q_array(1).... etc?

From:

--Process to write data into the register file
process(CLK)
begin
if clk'event and clk = '1' then
for i in 0 to 7 loop
Q_array(i) <= DR_Data;
end loop;
end if;

It appears all elements in Q_array are the same, which is why they're removing the copies.

 

[beer]

Originally posted by: TuxDave
Can you copy and paste the lines which generates values for Q_array(0) and Q_array(1).... etc?

From:

--Process to write data into the register file
process(CLK)
begin
if clk'event and clk = '1' then
for i in 0 to 7 loop
Q_array(i) <= DR_Data;
end loop;
end if;

It appears all elements in Q_array are the same, which is why they're removing the copies.

OK, uh sorry. There is a write enable in the DFF that is one-hotted so it doesn't overrite unless it's enabled.

entity RegisterFile is
port(SR1, SR2, DR: in std_logic_vector(2 downto 0);
DR_data: in std_logic_vector(3 downto 0);
WE, CLK, RegSet, RegReset: in std_logic;
RegOut1, RegOut2: out std_logic_vector(3 downto 0));
end RegisterFile;


architecture Behavioral of DFF is
process(STN, RSTN, CLK)
begin
if RSTN = '0' then Q <='0';
elsif STN = '0' then Q <='1';
elsif CLK = '1' and clk'event then
if (WE='1') then
Q <= D;
end if;
end process;
end Behavioral;

 

[TuxDave]

Ugh.. my brain hurts. I see how your DFF works but I still don't see how where you use it in

--Process to write data into the register file
process(CLK)
begin
if clk'event and clk = '1' then
for i in 0 to 7 loop
Q_array(i) <= DR_Data;
end loop;
end if;

Sorry I can't be of more help. You said your simulations work fine, are you monitoring the contents of Q_array to verify that they are still unique?

 

[beer]

Alright, I just went ahead and yanked the entire structural design and replaced it with one 32-wide register and lots of tristates on the output to break it up into eight logical components. It works fine now, I think....

 

[sciencewhiz]

What's your synthesis engine?

 

[beer]

xilinx ise 6